TMS320F28379D: I2C Communication from Delfino to FPGA

We are working to establish I2C communication between a TMS320F28379D (Master) and an Altera / Intel FPGA (Slave).  The FPGA slave interface protocol is as follows:

Start (sent from master)
Byte 0: 7-bit slave addr + R/W' bit = 1 (sent from master)
Bytes 1-4: Protocol specific data (sent from master)
Bytes 5-6: Protocol specific data (sent from slave)
NAK (sent from master)
Stop (sent from master)

Also, not listed above, are the appropriate ACKs between each byte.

This does not appear to be compatible with 7-bit or 10 bit addressing modes so we are using the free data format.

We have performed tests where we can send the start bit and 5 bytes of information to the slave (with appropriate ACKs from the slave) but we have not been able to cause the master to send clocks to receive the last two bytes without it inserting another start signal.

Is there a way to implement this protocol of Start - Send 5 bytes - Receive 2 bytes - NAK - Stop, without having to insert the start signal between the send and receive?

Thanks.