Hi champs.
I have some questions about FMC.
At TRM P121-122
"A single FMC controls both Bank0 and Bank1. The CPU interfaces with the FMC, which in turn interfaces with Bank0 and Bank1 and the shared pump, to perform erase or program operations, to read data, and execute code from these flash banks.
There is a state machine in FMC which generates the erase/program sequences in hardware. This simplifies the Flash API software which configures control registers in the FMC to perform flash erase and program operations. Please refer to the TMS320F28004x Flash API Reference Guide for more information for details on Flash API."
My understands are
1. FMC can execute Flash ERASE and PROGRAM without CPU. (Instruction from CPU)
2. The CPU can execute other instructions while FMC is executing ERASE/PROGRAM.
3. The FMC checks the ECC check bit. But FMC can not do VERIFY executed.
4. Also, even if BANK is the same, FMC can be executed ERASE/PROGRAM when SECTOR is different.
5. FMC interrupts the CPU when execution ERASE/PROGRAM is completed.
Are these correct?
Please tell me if there are other features.
Regards,
Shinji Ueda