TMS320F28069: Clear CAN mailbox interrupt

Celine Le Berre

Part Number: TMS320F28069

Hello everyone,

my question can seem pretty simple but I would like someone to confirm the way to clear a CAN mailbox interrupt as I've found confusing information in datasheet and example code.

I am using the eCana in SCC configuration with Mbx [0-9] configured in Rx and the others in Tx.

In the Rx Can Callback, I clear the Mailbox interrupt as following:

EALLOW;

ECanaShadow.CANRMP.all = ECanaRegs.CANRMP.all;

ECanaShadow.CANRMP.all |= bit;

ECanaRegs.CANRMP.all = ECanaShadow.CANRMP.all;

EDIS;

Is it the right way to do ?

The datasheet content which confuse me are below:

2.7 Received-Message-Pending Register (CANRMP)

The bits in the CANRMP and the CANRML registers are cleared by a write to register CANRMP, with a 1 at the corresponding bit location.

So it is reset by writing 1 (‘inverted’ reset).

3.2.4 Receiving a Message

Before the CPU reads the message from the mailbox, it should first clear the RMP bit (RMP.3 = 1).

It seems there is double meaning in the articles 1.5.2 and 3.2.4 (before and after reading).

over 7 years ago

0 Hareesh Janakiraman over 7 years ago

TI__Guru* 95315 points

You are correct that a write of "1" will clear the corresponding RMP bit. For this reason, when you write to RMP register, all bits other than the one you actually want to clear must be masked (0). You must AND the appropriate bit-mask. Also note that you can use the ".bit" definition while writing to the shadow register. For example, if you initialize the shadow RMP register to all zeros, you can selectively make a chosen bit as "1" and write the shadow value into CANRMP.

Clearing the RMP first gives raise to the chance that a message-overwrite may go undetected.

0 Celine Le Berre over 7 years ago in reply to Hareesh Janakiraman

Prodigy 90 points

Thanks Hareesh for confirming.

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TMS320F28069: Clear CAN mailbox interrupt