TMS320F28377D: TMS320F28377D: usage of SCID on CPU2

Hi Nicola,

When using GPIO as peripheral function (like in this case as SCI), you don't have to change the core select for that. Changing peripheral ownership takes cares of that. So following is not needed.

Configuration of GPIOCtrlRegs.GPCSEl4.BIT.GPIO93 =0x2
Configuration of GPIOCtrlRegs.GPCSEl4.BIT.GPIO94 =0x2

It should not cause any issue but I would remove that.

Please confirm that clock to SCID is enabled from CPU2. PCCLKCRx registers need to be enabled from the core which have ownership of the peripheral.

Regards,
Vivek Singh

Hi Nicola, Is this issue resolved?

Hi Vivek,

I removed the following lines of code you reported me to be useless:

 

Configuration of GPIOCtrlRegs.GPCSEl4.BIT.GPIO93 =0x2

Configuration of GPIOCtrlRegs.GPCSEl4.BIT.GPIO94 =0x2

 

I confirm that with the CPU2 I make all the configurations of the necessary registers, among which the writing of the clock register (CpuSysRegs.PCLKCR7).

In our project we have developed drivers for the configuration of SCI devices that perform all the setups that must be performed by the CPU that wants to use the SCI.

We have tested the operation of the driver for both the SCIA and the SCID: the CPU1 is able to use both the SCIA and the SCID.

But when we try to use one of the two SCIs on the CPU2, for example the SCID, the SCID is not able to use it.

The operations that are executed by the CPU1 to enable the use of the SCID by the CPU2 are as follows:

//rx
GPIO_IoctlMux(94U, 6U);
//tx
GPIO_IoctlMux(93U, 6U);
GPIO_IoctlOptions(93U, 1U, GPIO_FLAG_QUALTYPE_ASYNC, 0U);

CORE_Eallowext();
CpuSysRegs.PCLKCR1.bit.EMIF1 = 1;
DevCfgRegs_377D->CPUSEL5.bit.SCI_D = USED_BY_CPU2; //#define USED_BY_CPU2	(1U)
CORE_Edisext();

The CPU2, before the driver-specific initializations, execute the following operations:

/** Initialize the PIE control registers to their default state.
* The default state is all PIE interrupts disabled and flags
* are cleared.
*/
if (result == RET_OK) {
	result = CORE_InitPieCtrl();
}

/** Initialize the PIE vector table with pointers to the shell Interrupt
* Service Routines (ISR).
* This will populate the entire table, even if the interrupt
* is not used.
*/
if (result == RET_OK) {
	result = CORE_InitPieVectTable();
}

CORE_Eallowext();
	CpuSysRegs.PCLKCR1.bit.EMIF1 = 1;
CORE_Edisext();

On the basis of our debugging operations we have noticed that all the configurations carried out are successful and are written correctly in the registers of the CPU1 and of the CPU2. What we have noticed is that the serial interrupt routine related to the SCID used by the CPU2 is never executed. We also noticed that the CPU2 vectorTable does not seem to be updated. What can we have to do?

 

By the way, do restrictions about the peripheral usage by the CPU2 exist?

Thanks a lot,

Nicola

Hi Nicola,

We do not have any restriction on usage by CPU2.

We also noticed that the CPU2 vectorTable does not seem to be updated. What can we have to do?

If vector table is not updated then you'll not notice the interrupt. You have pie vector table initialization inside if condition. Have you checked that this condition is TRUE (RET_OK) ? Seems like some handshake issues between CPU1 and CPU2.

Regards,

Vivek Singh

Were you able to resolve this issue?