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CCS/TMS320F28377S: program not fitting into available memory.

Milarepa
Expert 1680 points
Part Number: TMS320F28377S


Tool/software: Code Composer Studio

I am getting the following error:

<Linking>
"../28377S_RAM_lnk.cmd", line 58: error #10099-D: program will not fit into available memory. placement with alignment/blocking fails for section ".cinit" size 0x2e1 page 0. Available memory ranges:
RAMM0 size: 0x2de unused: 0x0 max hole: 0x0
error #10010: errors encountered during linking; "VC_SCIM.out" not built

I have made the following changes :

RAMM0            : origin = 0x000122, length = 0x0012DE //0x0002DE to  0x0012DE

I am getting the following error:

C28xx_CPU1: GEL Output: 

Memory Map Initialization Complete
C28xx_CPU1: Loader: One or more sections of your program falls into a memory region that is not writable. These regions will not actually be written to the target. Check your linker configuration and/or memory map.

I need to write some more algorithms in my code and hence need more space.

Any suggestions?

  • 0
    Guru 30330 points
    Hello Shyam,

    You are on the right track as to modifying the linker file, however you must align with the available memory on the device. Please read through the Linker Command File Wiki page.
    processors.wiki.ti.com/.../Linker_Command_File_Primer

    You will also need to consult your device memory map to ensure that you are combining/modifying the map to align with what is avaialable.

    -Mark
  • 0 in reply to Mark Labbato
    Expert 1680 points

    Thank you.
    I do not have much background in these. Where can i find the available memory on the device.
    Please guide me on how to do these.

  • 0 in reply to Milarepa
    Guru 30330 points
    Shyam,

    The Memory map of the device can be found in the datasheet.
    www.ti.com/.../detailed-description -Section 6.3 Memory

    Thanks,
    Mark
  • 0 in reply to Mark Labbato
    Expert 1680 points

    I tried to modify the linker file as:

     RAMM0            : origin = 0x000122, length = 0x0002DE             to             0x0003DE  

    but when i clicked RUN, it generated an error, saying

    No source available for "0x3fe493"

    Memory map gives the following information about RAMM0:

    M0 RAM           1K × 16             0x0000 0000              0x0000 03FF

    Please let me know how to proceed.

    Thanks

  • 0 in reply to Milarepa
    TI__Mastermind 19810 points
    Shyam,
    are you trying to run a TI provided example modified as per your needs? You have to be careful when increasing the size of a memory section in linker command file to fit in a program segment. First you have to check if the memory range is available and the device memory map that Mark pointed to will help with that and second you will have to make sure that the memory range (start address + length) doesn't overlap with another section.

    Expecting that you are starting with a TI provided example as reference and associated TI provided linker command files as a reference, now if your .cinit won't fit into available M0 RAM, what you did is you increased the M0 RAM but is it over lapping with M1 RAM? You didn't provide your entire linker command file so I cannot tell exactly what is wrong.

    Usually to fit in a program segment
    > you can move the segment linking to a bigger memory section defined in linker command file, for ex: you can move .cinit to a L0 RAM or L1 RAM etc.

    OR
    > You can combine two RAM sections into a single one, by modifying the linker command file , like instead of having an entry of length 0x1000 for each Lx RAM you can do L0L1 RAM with a length of 0x2000 and link your program segment here. I'm just giving an example here, you will have to look at your device datasheet memory map to see what RAMs are available.

    Take a look at C2000 compiler reference manual ,section 4.3.6 talks about allocating sections to memory.
    www.ti.com/.../spru514o.pdf

    Also refer to Assembly language tools guide, section 2.3 and 2.4
    www.ti.com/.../spru513o.pdf

    if you have embedded SW development experience with any other MCU, this should be similar to what you already know.

    On the other question of "No source available for "0x3fe493" , this location refers to device boot ROM. Check device boot ROM chapter of the device TRM , section 3.9.2 , table 3-11. As per the table it looks like your application ended up in an iTRAP ISR, which means there was an illegal instruction fetch and which is most probably because your linker command file is not proper. This could be because of one of the points I mentioned above.

    Hope this helps.

    Best Regards
    Santosh Athuru
  • 0 in reply to Santosh Athuru
    Expert 1680 points

    Thanks. I dont have much background in these.


    MEMORY
    {
    PAGE 0 :
    /* BEGIN is used for the "boot to SARAM" bootloader mode */

    BEGIN : origin = 0x000000, length = 0x000002
    RAMM0 : origin = 0x000122, length = 0x0002DE
    RAMD0 : origin = 0x00B000, length = 0x000800
    RAMLS0 : origin = 0x008000, length = 0x000800
    RAMLS1 : origin = 0x008800, length = 0x000800
    RAMLS2 : origin = 0x009000, length = 0x000800
    RAMLS3 : origin = 0x009800, length = 0x000800
    RAMLS4 : origin = 0x00A000, length = 0x000800
    RAMGS14 : origin = 0x01A000, length = 0x001000
    RAMGS15 : origin = 0x01B000, length = 0x001000
    RESET : origin = 0x3FFFC0, length = 0x000002

    PAGE 1 :

    BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
    RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
    RAMD1 : origin = 0x00B800, length = 0x000800


    RAMLS5 : origin = 0x00A800, length = 0x000800

    RAMGS0 : origin = 0x00C000, length = 0x001000
    RAMGS1 : origin = 0x00D000, length = 0x001000
    RAMGS2 : origin = 0x00E000, length = 0x001000
    RAMGS3 : origin = 0x00F000, length = 0x001000
    RAMGS4 : origin = 0x010000, length = 0x001000
    RAMGS5 : origin = 0x011000, length = 0x001000
    RAMGS6 : origin = 0x012000, length = 0x001000
    RAMGS7 : origin = 0x013000, length = 0x001000
    RAMGS8 : origin = 0x014000, length = 0x001000
    RAMGS9 : origin = 0x015000, length = 0x001000
    RAMGS10 : origin = 0x016000, length = 0x001000
    RAMGS11 : origin = 0x017000, length = 0x001000
    RAMGS12 : origin = 0x018000, length = 0x001000
    RAMGS13 : origin = 0x019000, length = 0x001000

    }


    SECTIONS
    {
    codestart : > BEGIN, PAGE = 0
    ramfuncs : > RAMM0 PAGE = 0

    #ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
    .TI.ramfunc : {} > RAMM0, PAGE = 0
    #endif
    #endif

    .text : >>RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0
    .cinit : > RAMM0, PAGE = 0
    .pinit : > RAMM0, PAGE = 0
    .switch : > RAMM0, PAGE = 0
    .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

    .stack : > RAMM1, PAGE = 1
    .ebss : > RAMLS5, PAGE = 1
    .econst : > RAMLS5, PAGE = 1
    .esysmem : > RAMLS5, PAGE = 1

    ramgs0 : > RAMGS0, PAGE = 1
    ramgs1 : > RAMGS1, PAGE = 1
    }

    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */

    Please let me know what should I do so that i can write some more algorithms without hitting this problem again.

    Thanks again !!

  • 0 in reply to Santosh Athuru
    TI__Mastermind 19810 points

    Also refer to the below link, Mark also referred to this in his suggestion above. The below wiki talks about how to allocate to multiple memory ranges or how to split a segment across multiple memory ranges.

    http://processors.wiki.ti.com/index.php/Linker_Command_File_Primer

    Best regards
    Santosh Athuru

  • 0 in reply to Milarepa
    TI__Mastermind 19810 points
    The linker command file looks good to me, if you are not able to fit .cinit, try allocating .cinit to RAMLS5, instead of RAMM0?

    If that doesn't work, inspect the memory map (*.map file) file generated to see if any of the LS0 to LS4 are unused and move that memory to PAGE 1, and link .cinit to that page.

    As your application grows see if you can link code to flash, that will free up your RAM usage.

    Best Regards
    Santosh Athuru
  • 0 in reply to Santosh Athuru
    Expert 1680 points

    Thanks.

    What i find is i can increase the body of the code without hitting this problem, but as soon as i declare some variables, this memory issue pops up.

  • 0 in reply to Milarepa
    TI__Mastermind 19810 points

    Shyam,

    as mentioned in above posts from me, just move the linking of the section that fails to fit in the available memory to a bigger RAM section. I'm not sure if you understood the solutions suggested above or not. 

    Let us know if we can be of any further help.

    Best Regards

    Santosh Athuru

  • 0 in reply to Santosh Athuru
    Expert 1680 points

    Could you please show an example. I have been trying without any success.

    Regards,

    R Nair

  • 0 in reply to Milarepa
    Guru 30330 points
    R Nair,

    Are you still receiving the same error about .cinit not fitting in the available memory?
    Perhaps you take a look at the Memory Allocation tool inside of CCS. if you are using CCSv7 this is located in View-> Memory Allocation near the bottom of the list. It will give you a visual of where your memory is used after the build. It will show the sections which were not able to be placed if there was an error. Really you can place most sections anywhere in the memory space.

    For an example you can check out the Delfino F28379D Multi-day workshop. Lab 2 specifically deals with linker command files.
    processors.wiki.ti.com/.../C2000_Multi-Day_Workshop

    Thanks,
    Mark
  • 0 in reply to Mark Labbato
    Guru 30330 points
    R Nair,

    It has been a few days since you last replied. Are you still working on this issue? I am going to mark this post as closed. If you have further questions, please let us know.

    Thanks,
    Mark