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TMS320F28377S: ADC PPPB latches ADCyEVTx

EK
Expert 2530 points

Part Number: TMS320F28377S

Hi

Unfortunately this thread https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/631741?tisearch=e2e-quicksearch seems being locked, I can't reply.

First of all I'd like to see documentation fixed regarding missing CBCEN bit.

Contrary to what Devin Cottier stated in above mentioned thread, PPB ADCAEVT0 seems being latched and ePWM CBC trip zone stays active until I write "1" to corresponding bit position in ADCEVTCLR register. I'm using revision C silicon. According to PPB diagram in TRM, ADCAEVT0 should pulse and not latch.

Edward

  • 0
    TI__Genius 16085 points
    Hi EK,

    A TI engineer has been assigned to help with your issue. The response may be delayed due to the holiday. Thanks for your patience.

    Best regards,
    Chen
  • 0 in reply to Chen Jiang ti
    TI__Guru 60865 points
    Hi EK,

    I'm looking into this, but it may take a few days for an answer still.
  • 0 in reply to Devin Cottier
    TI__Guru 60865 points

    Hi EK,

    Sorry for the delay, and the confusion.

    On F28377x Revisions 0, A, and B the following erratum applies:

    • ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital Compare Submodule
      • The ADCxEVT trigger to the ePWM digital compare submodule may not be detected by the ePWM.

    The reason for this errata is that the PPB would produce a pulse output only, which wasn't long enough to consistently trigger the ePWM.

    Now on F28377x Rev. C, this was fixed and the output is now latched.  Contrary to what I said in the referenced thread, you indeed must clear the PPB status bit(s) before the ePWM trip zone can be cleared.

    Now on the F2804x device, there is an additional feature: cycle-by-cycle tripping (CBCEN bit).  Setting this bit will cause the PPB flags to be cleared automatically when new ADC results are loaded if they don't exhibit the trip conditions.  This feature is not present on F28377x.

  • 0 in reply to Devin Cottier
    Expert 2530 points
    Hi Devin,

    Thank you very much for explanation. When this is going to land in Reference Manual and/or Errata document changes? It is still not documented!!! Can I assume that next silicon revision will work the same like rev. C?

    Thanks,
    Edward
  • 0 in reply to EK
    TI__Guru 60865 points
    Hi EK,

    The next documentation release should have these changes. All future revisions would support the current functionality.