Hi,
my customer is testing the board TMDSHVRESLLCKIT.
PWMDRV_LLC_1ch_UpCntDB_Comp.asm code is as below:
;=============================
PWMDRV_LLC_1ch_UpCntDB_Compl .macro
;=============================
MOVW DP, #_PWMDRV_LLC_1ch_UpCntDB_Compl_Duty2 ; load DP for net pointer
MOVL XAR0, @_PWMDRV_LLC_1ch_UpCntDB_Compl_Duty2 ; Load net pointer address to XAR0
MOVL XAR1, @_PWMDRV_LLC_1ch_UpCntDB_Compl_Period2 ; Load net pointer address to XAR1
MOVL ACC, *XAR1
SFR ACC, #14 ; ACC>>14: AL = Period (Q10)
MOVW DP, #_EPwm2Regs.TBPRD
MOV @_EPwm2Regs.TBPRD, AL ; Update period register
MOVL XT, @_EPwm2Regs.TBPRD ; 注意这里是MOVL指令,即XT=TBPRD<<16
QMPYL ACC, XT, *XAR0 ; ACC = (I16Q16) * (I8Q24) = (I24Q40): upper 32-bits -> ACC = (I24Q8)
SFR ACC, #8 ; ACC>>8: AL = Duty*Period (Q16)
SUB @T, AL ; T = Period - Duty*Period
MOVW DP, #_EPwm2Regs.CMPA
MOV @_EPwm2Regs.CMPA.half.CMPA, T ; Update CMPA
ROR ACC ; AL = Duty*Period/2
SUB ACC, #13 ; compensate for 1st sample bug
ADD @T, AL
MOVW DP, #_EPwm2Regs.CMPB
MOV @_EPwm2Regs.CMPB, T ; Update CMPB = Duty midpoint
MOVL ACC, *XAR1
SFR ACC, #14 ; ACC>>14: AL = Period (Q10)
MOVW DP, #_EPwm2Regs.DBFED
SUB AL, @_EPwm2Regs.DBFED ; use FED value to create Falling Edge Margin (advance falling edge)
MOVW DP, #_EPwm2Regs.TBPRD
MOV @_EPwm2Regs.TBPRD, AL ; Update period register (with FEM)
.endm
The question is:
1. Why there is no "EALLOW" when writing to registers such as EPwm2Regs.TBPRD? And by single step with CCS3.3, EPwm2Regs.TBPRD is not updated
2. Is "CMPB= 0.5*period*duty-13+period-duty*period=period-0.5*period*duty-13", in the comment it's said that 13 is compensated for 1st sample bug, what's sample bug, and why it's 13?
