I have an application where I would like to setup two SPI controllers for two external devices (one master IC and one slave IC). My preferred solution is that SPI-A would be a CPU1 master controller with DMA support and SPI-B would be a CLA1 slave controller FIFO. I see that the Peripheral Frame 2 (CpuSysRegs.SECMSEL.bit.PF2SEL) must be set either to CLA or DMA as the secondary master. So does this mean that I can't allow the DMA to have access to SPI-A master concurrently while CLA has access to SPI-B slave?