Hi,
I am running the DSP @150 MHz as an SPI slave. I find some confusion about the SPI clock frequency limits in the documentation.
The datasheet SPRS439N:
- (a) Table 5-34 in pg. 66 states that maximum SPICLK frequency (when Clock Phase = 0) can be LSPCLK/4, which would mean 75 MHz / 4 = 18.75 MHz. But then there is a note (3) saying that the maximum frequency is hard fixed and equal to 12.5 MHz.
- (b) Table 5-35 in pg. 68 states that maximum SPICLK frequency (when Clock Phase = 1) can be LSPCLK/8, which would mean 75 MHz / 8 = 9.375 MHz. But then there is a note (3) saying the same as before, that the maximum frequency is hard fixed and equal to 12.5 MHz.
From this I would understand that the effective limit is the lower of the two. So in case (a), the limit is 12.5 MHz, and in case (b), the limit is 9.375 MHz.
But! The SPI user manual SPRUEU3A states:
- "The SPI is no longer limited to a maximum transmission rate of LSPCLK/8 in slave mode. The maximum transmission rate in both slave mode and master mode is now LSPCLK/4",
which contradicts the case (b). Yet the datasheet was last revised in 2016, while SPI manual was last revised in 2009.
Q1: which information is correct for (b) case?
Q2: is my assumption, that 12.5 MHz is a hard limit for this DSP, correct?
Regards,
Dainius
