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TMS320F28075: How to interrupt on the completion of ADC BURST mode?

Aaron Needles
Intellectual 615 points

Part Number: TMS320F28075

Hi,

I would like to sample a set of ADC inputs in BURST mode and then interrupt the processor when the last one is complete. Is there a mechanism that can do this?  I am currently getting the interrupt right after the first sample is complete, which is too early to read all of the samples.

Thanks,

       Aaron

Here's my setup code so far:

// From SPRUHM9D table 9-22
#define BURSTTRIGSEL__EPWM1_ADCSOCA 5
//

//Select the channels to convert
//
EALLOW;
AdcaRegs.ADCBURSTCTL.bit.BURSTEN = 1;
AdcaRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = BURSTTRIGSEL__EPWM1_ADCSOCA;
AdcaRegs.ADCBURSTCTL.bit.BURSTSIZE = 7;

// SOC0
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 1; // FSR0
AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps;
// SOC1
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 2; // FSR1
AdcaRegs.ADCSOC1CTL.bit.ACQPS = acqps;
// SOC2
AdcaRegs.ADCSOC2CTL.bit.CHSEL = 3; // FSR2
AdcaRegs.ADCSOC2CTL.bit.ACQPS = acqps;
// SOC3
AdcaRegs.ADCSOC3CTL.bit.CHSEL = 4; // FSR3
AdcaRegs.ADCSOC3CTL.bit.ACQPS = acqps;
// SOC4
AdcaRegs.ADCSOC4CTL.bit.CHSEL = 5; // FSR4
AdcaRegs.ADCSOC4CTL.bit.ACQPS = acqps;
// SOC5
AdcaRegs.ADCSOC5CTL.bit.CHSEL = 6; // FSR5
AdcaRegs.ADCSOC5CTL.bit.ACQPS = acqps;
// SOC6
AdcaRegs.ADCSOC6CTL.bit.CHSEL = 7; // FSR6
AdcaRegs.ADCSOC6CTL.bit.ACQPS = acqps;
// SOC7
AdcaRegs.ADCSOC7CTL.bit.CHSEL = 8; // FSR7
AdcaRegs.ADCSOC7CTL.bit.ACQPS = acqps;

AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // Set end of SOC? to set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Clear flag
EDIS;

  • 0
    Genius 3050 points

    Hello, Aaron

    You need to set AdcaRegs.ADCINTSEL1N2.bit.INT1SEL to "7", because your last sample is SOC7

    Each SOC starts a conversion and generates EOC (End-of-Conversion), when conversion or sampling is over. Refer to SPRUHM9, chpater 9 "ADC" and particularly page 1304-1305 about ADCINTSELxNy registers. Also pay attention to chapters 9.2.1 with ADC timings and chpater 9.1.8 about EOC pulse. You can set EOC signal to be generated right after "Sample-and-Hold" stage, or after conversion (refer to timing diagram).