TMS320F28027F: Complementary PWM Signals with HRPWM

Jeff,

you should be able to use PWM1A and PWM2A to do this, note that the sync chain is not high resolution, so you should expect some jitter between the two signals.

See this post: https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/62564f 

I don't have an example of complementary HRPWM channels. You should be able to achieve complementary signals with varying edge modes, control modes or shadow modes. The PWM reference guide will be the biggest help here. 

When implementing this if you run into a more pointed question I maybe able to help more.

Hope it helps!
Cody 

Cody,

Thank you for your response. Do you believe the jitter will be significant with respect to my desired frequency of 750 kHz?

I've been trying to follow the HRPWM reference guide but am a bit stuck. I'll attempt to elaborate my uncertainty further. 

I'm trying to synchronize the ePWM1A and ePWM2A channels. Ideally, I'd like to be able change the phase of one with respect to the other by modifying a single parameter in the code. I am attempting to achieve single phase shift control of a dual active bridge (DAB) dc/dc converter. 

I used the code base from the 2802xHRPWM example and modified it as necessary. Here is the relevant code I have:

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Uint16 period = 80;

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;

EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 0x1;
EPwm1Regs.TBCTL.bit.PHSEN = 0x1;
EPwm1Regs.HRPCTL.bit.HRPE = 0x1;

EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set Shadow load

EPwm1Regs.TBPRD = period-1; // PWM frequency = 1 / period
EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
EPwm1Regs.CMPB = period / 2; // set duty 50% initially
EPwm1Regs.TBPHS.all = 0;
EPwm1Regs.TBCTR = 0;

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; // EPwm1 is the Master
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;

EALLOW;

EPwm1Regs.HRCNFG.all = 0x0;
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP; //MEP control on Rising edge
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_PHS;
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD;
EDIS;

EPwm2Regs.HRPCTL.bit.TBPHSHRLOADE = 0x1;
EPwm2Regs.TBCTL.bit.PHSEN = 0x1;
EPwm2Regs.HRPCTL.bit.HRPE = 0x1;

EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set Shadow load

EPwm2Regs.TBPRD = period-1; // PWM frequency = 1 / period
EPwm2Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
EPwm2Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
EPwm2Regs.CMPB = period / 2; // set duty 50% initially
EPwm2Regs.TBPHS.all = 50;
EPwm2Regs.TBCTR = 0;

EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // EPwm1 is the Master
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;

EALLOW;

EPwm2Regs.HRCNFG.all = 0x0;
EPwm2Regs.HRCNFG.bit.EDGMODE = HR_BEP; //MEP control on Rising edge
EPwm2Regs.HRCNFG.bit.CTLMODE = HR_PHS;
EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD;
EDIS;

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

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What I see on the scope after uploading the code is the two 750 kHz signals in phase.

I set EPwm2Regs.TBPHS.all = 50 as an arbitrary value to test whether it would adjust the phase between the two. I could not figure out precisely which register controls the phase value between the two. Could you help me with that? 

Thank you very much,

Jeff