TMS320C28346: Rise Time Requirement for Clock Input

Gerald Bobe

Hello,

I have an existing Design with the TMS320F28346. During a Review we found an issue with the clock input.

We are running the unit with an external 25MHz clock at XCLKIN input. The datasheet requirement for the rise/fall Time (Chapte 6.8 No. C9,C10) is 4ns maximum.
Actually our actual design gets only 6ns at that pin. Is it possible to run the controller with the reduced rise/fall time?

We actually don't see any problems there, and quarz oszillators with 25MHz/4ns are very rare and hard to source.

Thanks for Your help and ideas,

Gerald

over 8 years ago

0 Hareesh Janakiraman over 8 years ago

TI__Guru* 95315 points

Gerald,
I am looking into this question. I may have to run this with the Design folks.

0 Hareesh Janakiraman over 8 years ago in reply to Hareesh Janakiraman

TI__Guru* 95315 points

Gerald,
Could you please reach out to me through the TI-FAE supporting you?

0 Ramesh Ramamoorthy over 8 years ago in reply to Hareesh Janakiraman

TI__Mastermind 27240 points

Gerald,
Are you being helped offline. If so, since the thread is not active, pls consider closing it.

0 Gerald Bobe over 8 years ago in reply to Ramesh Ramamoorthy

Prodigy 50 points

Its a TMS320C28346ZFET SN-IGA96TW GI.

But anyway, we have this in misc. devices over all production lots since 2013.

Actually we have no solution.

We are looking for a clock sulution with more driving power to get in the 4ns range, but that is very hard with the given pcb due to the footprint of the clock generator (5x7 SMD) and the actual series resistor of 22R placed in an array. I cant just add buffer.

We checked other potetial causes (code, peripherals an ti errata) and all code an connections follow the recommendations as diescribed.

Are there any more ideas?

Gerald

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320C28346: Rise Time Requirement for Clock Input