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TMS320F28377D: Maximum ADC sample rate

IainRist
Intellectual 711 points
Part Number: TMS320F28377D

There is an inconsistency within the F2837xD datasheet (sprs880h) concerning the maximum ADC sample rate that has a material difference on my project:

  1. table 3-1 states the maximum sample rate is 3.5 Msps and the minimum ADC conversion duration is 290 ns.
  2. table 5-43 states the minimum acquisition window is 75 ns, 15 clock cycles for a SYSCLK of 200 MHz.
  3. table 5-49 states the ADC conversion takes 41 SYSCLK cycles when the ADCCLK is 50 MHz and SYSCLK is 200 MHz.

Points 2 and 3 give me:

  1. a minimum conversion duration of 56 SYSCLK cycles
  2. a minimum conversion duration of 280 ns for SYSCLK at 200 MHz
  3. a maximum sample rate of 3.57 Msps

Is the minimum conversion duration 280 ns as calculated from the datasheet, or 290 ns as stated in the datasheet? If it is the latter, what is the source of the inconsistency in figures?

  • 0
    TI__Guru 60865 points

    Hi IainRist,

    Table 5-49 should be correct.  

    Using 12-bit mode with 200MHz SYSCLK and 50MHz ADCCLK:

    • Minimum S+H is 75ns / 15 SYSCLK cycles
    • End of S+H to start of next S+H is 41 SYSCLK cycles = 205 ns
    • Total conversion time when determining sample-rate of back-to-back continuous conversions = 1 / (205ns + 75ns) = 3.5714MSPS
    • Trigger to output latency of the first conversion is:
      • 2 sysclks for the trigger to propagate and latch + 15 cycles for the S+H + 44 cycles for the conversion and results to latch = 61 cycles / 305ns
      • Subsequent results using back-to-back continuous conversions should be available every 56 cycles / 280ns

    We'll update the value in the features table.