TMS320F28377S: CAN FIFO configuration

In RM, p21.10.5:

"The EoB bit of all message objects of a FIFO buffer except the last one have to be programmed to zero."

Or, all FIFO RX mailboxes except the last one should have EoB=0, and the last FIFO RX mailbox - EoB=1.

I'm using 3 RX FIFO's with 3 different acceptance filters. I can't guarantee it's perfectly correct, but seems working well. Here's an excerpt from my Init routine:

#define FIFOR0 1 // FIFO 0 starts at mailbox 1
#define FIFOR1 9 // FIFO 1 at MB 9
#define FIFOR2 11 // FIFO 2 at MB 11

//FIFO MB initialization


for(iMsg = FIFOR0; iMsg < FIFOR1; iMsg++)
{
CANM.CAN_IF1ARB.bit.MsgVal = 1; // message is used
CANM.CAN_IF1ARB.bit.Xtd = 1; // extended id
CANM.CAN_IF1ARB.bit.Dir = 0; // receive mb
CANM.CAN_IF1ARB.bit.ID = <some acceptance id pattern>;

#if CAN_FORWARDONLY
CANM.CAN_IF1MSK.all = 0; // accept everything
#else
CANM.CAN_IF1MSK.bit.MXtd = 1; // mask extended bit
CANM.CAN_IF1MSK.bit.MDir = 0; // don't accept send messages
CANM.CAN_IF1MSK.bit.Msk = <some acceptance mask value>;
#endif

CANM.CAN_IF1MCTL.all = (1<<12/*UMask*/)|(1<<10/*RxIE*/); // All MB, except last one have EoB=0
if(iMsg == (FIFOR1-1))
CANM.CAN_IF1MCTL.bit.EoB = 1; // end of fifo


CANM.CAN_IF1CMD.all =
(
0x80 * 1 /*DIR*/
| 0x40 * 1 /*Mask*/
| 0x20 * 1 /*Arb*/
| 0x10 * 1 /*Control*/
| 0x08 * 1 /*ClrIntPnd*/
| 0x04 * 0 /*TXRQST*/
| 0x02 * 0 /*DATA_A*/
| 0x01 * 0 /*DATA_B*/
) * 0x10000ul | iMsg;

while(CANM.CAN_IF1CMD.bit.Busy)
{
}
CANM.CAN_IF1CMD.all = 0;
}

for(iMsg = FIFOR1; iMsg < FIFOR2; iMsg++)
{
CANM.CAN_IF1ARB.bit.MsgVal = 1; // message is used
...


Regards,
Edward