TMS320F28027F: Cannot generate phase shifted PWM

Jeff Hensal40

Hello,

I am having difficulty generating a phase shift between the PWM channels 1 and 2. I've been trying to follow the example in the ePWM Ref Guide "Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter", but I cannot get the code to compile as there are errors stating:

1) "EPwm2Regs.TBPHS = 1200-300;" cannot be of type int

2) "EPwm1Regs.CMPA = 600;" cannot be of type int.

I tried changing 1) to "EPwm2Regs.TBPHS.all = 1200-300;" and 2) to "EPwm1Regs.CMPA.all = 600;" to get the compiler to stop complaining, but then I do not observe any output from the GPIO0 (ePWM1A) or GPIO2 (ePWM2A). I have already set up the GPIOs separately in the code (multiplexed them with PWM modules and disabled pullup resistors) by means of a GPIO_Handle.

Can anyone provide assistance?

Thanks,

Jeff

over 8 years ago

0 Disona over 8 years ago

Genius 3050 points

Hello, Jeff.

The problem is in incorrect assignment.

TBPHS and CMPA registers are combination of two registers: for usual ePWM and for High-resollution ePWM. So TBPHS contains actually TBPHS.bit.TBPHS part and TBPHS.bit.TBPHSHR part (the last one is for high resolution). The same story with CMPA. And also HR part of each registers resides in bits 0:15 of 32-bit word "all". "Common" part resides in bits 16-31.

So when you write "CMPA.all = 0xFFF" you get "all = 0x0000 0FFF" - you actually write that number into lower 16 bits. As a result you get CMPAHR = 0xFFF and CMPA = 0.

The solution is to access regiters as "CMPA.bit.CMPA" and "TBPHS.bit.TBPHS". Could you try it please?

0 Jeff Hensal40 over 8 years ago in reply to Disona

Prodigy 230 points

Disona,

Thank you, I was able to achieve phase shift when setting TBPHS.half.TBPHS to an integer value. However, I still have one issue.

I believe I have ePWM1A and ePWM2A synchronized. But when I set:

EPwm2Regs.TBPHS.half.TBPHS = 0, I see that the signals are 8° out of phase.
EPwm2Regs.TBPHS.half.TBPHS = 1, I see that the signals are 4° out of phase.
EPwm2Regs.TBPHS.half.TBPHS = 2, I see that the signals are 0° out of phase, and thus are in phase.

I fear that this means I somehow messed up the synchronization between the PWM modules because when the phase between them is programmed to 0, they are still slightly out of phase. Does anyone know why I have this offset? My code is as follows:

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;

HRPWM1_Config(80); // ePWM1 target, Period = 80, yielding 750 KHz
HRPWM2_Config(80); // ePWM2 target, Period = 80

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

void HRPWM1_Config(Uint16 period)
{
EPwm1Regs.TBPRD = period-1; // PWM frequency = 1 / period
EPwm1Regs.CMPA.half.CMPA = period/2; // set duty 50% initially
EPwm1Regs.TBPHS.half.TBPHS = 0;
EPwm1Regs.TBCTR = 0;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR ;
}

void HRPWM2_Config(Uint16 period)
{
// ePWM1 register configuration with HRPWM

EPwm2Regs.TBPRD = period-1; // PWM frequency = 1 / period
EPwm2Regs.CMPA.half.CMPA = period/2; // set duty 50% initially
EPwm2Regs.TBPHS.half.TBPHS = 0;
EPwm2Regs.TBCTR = 0;
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
}
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------

0 Disona over 8 years ago in reply to Jeff Hensal40

Genius 3050 points

Hmm...

I think you can find some help in SPRUGE9 documentation (Piccolo EPWM User Manual) in part 2.2.2.3 "Time-base counter synchronization". It's said that when Epwm clocking speed equals SYSCLKOUT (and it is in your case since you set CLKDIV and HSPCLKDIV to "DIV1"), than synchronisation takes 2 cycles.

So this is just the value that gives you 9 cycles shift if you set TBPHS to 0: sync impulse is given when TBCTR1 is "0", but phase "0" will be loaded to TBCTR2 after 2 cycles, so TBCTR1 will be "2" at that moment. Also i think you actually see delays about 4.5 and 9 degrees, since 360/80 = 4.5.

I think that is... not even a problem, but special behavior of ePWM module =)

Hope this helps.

0 Cody Watkins over 8 years ago in reply to Disona

TI__Mastermind 42195 points

Jeff,
Disona is correct, there is a minor delay between the first PWM's Sync generation and synchronization of subsequent PWM modules. This delay is only between the first and the second synchronized module. If you sync PWM1 to PWM2 and then to PWM3 then the both PWM2 and PWM3 will have a 2 cycle delay behind PWM1. PWM3 will NOT be 2 cycles behind PMW2.

Regards,
Cody

0 Cody Watkins over 7 years ago in reply to Cody Watkins

TI__Mastermind 42195 points

Jeff,
I am closing the thread due to inactivity, feel free to start a new thread if you have more questions.

Regards,
Cody

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TMS320F28027F: Cannot generate phase shifted PWM