Part Number: TMS320F28377S
Other Parts Discussed in Thread: TMS320F28069
Tool/software: Code Composer Studio
I am trying to use the code for PI-CLA from C-2000 ware.When i set LS5 to be program memory from the code and then when i run the code the code run's into a section called illegal ISR and stops there
This is the code that i am using
/* Example_F28069_PI.c
*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* ALL RIGHTS RESERVED
*
*/
// header files
#include "DCL.h"
#include "cla_adc_fir32_shared.h"
#include "F28x_Project.h"
#include "stdio.h"
// function prototypes
interrupt void control_Isr(void);
// global variables
long IdleLoopCount = 0;
long IsrCount = 0;
float Duty=0;
// shared variables
#pragma DATA_SECTION(rk, "CpuToCla1MsgRAM")
#pragma DATA_SECTION(yk, "CpuToCla1MsgRAM")
#pragma DATA_SECTION(uk, "Cla1ToCpuMsgRAM")
#pragma DATA_SECTION(pi1, "Cla1DataRam1")
float rk = 0.25f;
float yk=0.05f;
float uk=0.00f;
DCL_PI pi1 = PI_DEFAULTS;
const struct PIE_VECT_TABLE PieVectTableInit = {
PIE_RESERVED_ISR, // Reserved
PIE_RESERVED_ISR, // Reserved
PIE_RESERVED_ISR, // Reserved
PIE_RESERVED_ISR, // Reserved
PIE_RESERVED_ISR, // Reserved
PIE_RESERVED_ISR, // Reserved
PIE_RESERVED_ISR, // Reserved
PIE_RESERVED_ISR, // Reserved
PIE_RESERVED_ISR, // Reserved
PIE_RESERVED_ISR, // Reserved
PIE_RESERVED_ISR, // Reserved
PIE_RESERVED_ISR, // Reserved
PIE_RESERVED_ISR, // Reserved
TIMER1_ISR, // CPU Timer 1 Interrupt
TIMER2_ISR, // CPU Timer 2 Interrupt
DATALOG_ISR, // Datalogging Interrupt
RTOS_ISR, // RTOS Interrupt
EMU_ISR, // Emulation Interrupt
NMI_ISR, // Non-Maskable Interrupt
ILLEGAL_ISR, // Illegal Operation Trap
USER1_ISR, // User Defined Trap 1
USER2_ISR, // User Defined Trap 2
USER3_ISR, // User Defined Trap 3
USER4_ISR, // User Defined Trap 4
USER5_ISR, // User Defined Trap 5
USER6_ISR, // User Defined Trap 6
USER7_ISR, // User Defined Trap 7
USER8_ISR, // User Defined Trap 8
USER9_ISR, // User Defined Trap 9
USER10_ISR, // User Defined Trap 10
USER11_ISR, // User Defined Trap 11
USER12_ISR, // User Defined Trap 12
ADCA1_ISR, // 1.1 - ADCA Interrupt 1
ADCB1_ISR, // 1.2 - ADCB Interrupt 1
ADCC1_ISR, // 1.3 - ADCC Interrupt 1
XINT1_ISR, // 1.4 - XINT1 Interrupt
XINT2_ISR, // 1.5 - XINT2 Interrupt
ADCD1_ISR, // 1.6 - ADCD Interrupt 1
TIMER0_ISR, // 1.7 - Timer 0 Interrupt
WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt
EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt
EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt
EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt
EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt
EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt
EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt
EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt
EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt
EPWM1_ISR, // 3.1 - ePWM1 Interrupt
EPWM2_ISR, // 3.2 - ePWM2 Interrupt
EPWM3_ISR, // 3.3 - ePWM3 Interrupt
EPWM4_ISR, // 3.4 - ePWM4 Interrupt
EPWM5_ISR, // 3.5 - ePWM5 Interrupt
EPWM6_ISR, // 3.6 - ePWM6 Interrupt
EPWM7_ISR, // 3.7 - ePWM7 Interrupt
EPWM8_ISR, // 3.8 - ePWM8 Interrupt
ECAP1_ISR, // 4.1 - eCAP1 Interrupt
ECAP2_ISR, // 4.2 - eCAP2 Interrupt
ECAP3_ISR, // 4.3 - eCAP3 Interrupt
ECAP4_ISR, // 4.4 - eCAP4 Interrupt
ECAP5_ISR, // 4.5 - eCAP5 Interrupt
ECAP6_ISR, // 4.6 - eCAP6 Interrupt
PIE_RESERVED_ISR, // 4.7 - Reserved
PIE_RESERVED_ISR, // 4.8 - Reserved
EQEP1_ISR, // 5.1 - eQEP1 Interrupt
EQEP2_ISR, // 5.2 - eQEP2 Interrupt
EQEP3_ISR, // 5.3 - eQEP3 Interrupt
PIE_RESERVED_ISR, // 5.4 - Reserved
PIE_RESERVED_ISR, // 5.5 - Reserved
PIE_RESERVED_ISR, // 5.6 - Reserved
PIE_RESERVED_ISR, // 5.7 - Reserved
PIE_RESERVED_ISR, // 5.8 - Reserved
SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt
SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt
SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt
SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt
MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt
MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt
MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt
MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt
DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt
DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt
DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt
DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt
DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt
DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt
PIE_RESERVED_ISR, // 7.7 - Reserved
PIE_RESERVED_ISR, // 7.8 - Reserved
I2CA_ISR, // 8.1 - I2CA Interrupt 1
I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2
I2CB_ISR, // 8.3 - I2CB Interrupt 1
I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2
SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt
SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt
SCID_RX_ISR, // 8.7 - SCID Receive Interrupt
SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt
SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt
SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt
SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt
SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt
CANA0_ISR, // 9.5 - CANA Interrupt 0
CANA1_ISR, // 9.6 - CANA Interrupt 1
CANB0_ISR, // 9.7 - CANB Interrupt 0
CANB1_ISR, // 9.8 - CANB Interrupt 1
ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt
ADCA2_ISR, // 10.2 - ADCA Interrupt 2
ADCA3_ISR, // 10.3 - ADCA Interrupt 3
ADCA4_ISR, // 10.4 - ADCA Interrupt 4
ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt
ADCB2_ISR, // 10.6 - ADCB Interrupt 2
ADCB3_ISR, // 10.7 - ADCB Interrupt 3
ADCB4_ISR, // 10.8 - ADCB Interrupt 4
CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1
CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2
CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3
CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4
CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5
CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6
CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7
CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8
XINT3_ISR, // 12.1 - XINT3 Interrupt
XINT4_ISR, // 12.2 - XINT4 Interrupt
XINT5_ISR, // 12.3 - XINT5 Interrupt
PIE_RESERVED_ISR, // 12.4 - Reserved
PIE_RESERVED_ISR, // 12.5 - Reserved
VCU_ISR, // 12.6 - VCU Interrupt
FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt
FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt
PIE_RESERVED_ISR, // 1.9 - Reserved
PIE_RESERVED_ISR, // 1.10 - Reserved
PIE_RESERVED_ISR, // 1.11 - Reserved
PIE_RESERVED_ISR, // 1.12 - Reserved
IPC0_ISR, // 1.13 - IPC Interrupt 0
IPC1_ISR, // 1.14 - IPC Interrupt 1
IPC2_ISR, // 1.15 - IPC Interrupt 2
IPC3_ISR, // 1.16 - IPC Interrupt 3
EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt
EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt
EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt
EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt
PIE_RESERVED_ISR, // 2.13 - Reserved
PIE_RESERVED_ISR, // 2.14 - Reserved
PIE_RESERVED_ISR, // 2.15 - Reserved
PIE_RESERVED_ISR, // 2.16 - Reserved
EPWM9_ISR, // 3.9 - ePWM9 Interrupt
EPWM10_ISR, // 3.10 - ePWM10 Interrupt
EPWM11_ISR, // 3.11 - ePWM11 Interrupt
EPWM12_ISR, // 3.12 - ePWM12 Interrupt
PIE_RESERVED_ISR, // 3.13 - Reserved
PIE_RESERVED_ISR, // 3.14 - Reserved
PIE_RESERVED_ISR, // 3.15 - Reserved
PIE_RESERVED_ISR, // 3.16 - Reserved
PIE_RESERVED_ISR, // 4.9 - Reserved
PIE_RESERVED_ISR, // 4.10 - Reserved
PIE_RESERVED_ISR, // 4.11 - Reserved
PIE_RESERVED_ISR, // 4.12 - Reserved
PIE_RESERVED_ISR, // 4.13 - Reserved
PIE_RESERVED_ISR, // 4.14 - Reserved
PIE_RESERVED_ISR, // 4.15 - Reserved
PIE_RESERVED_ISR, // 4.16 - Reserved
SD1_ISR, // 5.9 - SD1 Interrupt
SD2_ISR, // 5.10 - SD2 Interrupt
PIE_RESERVED_ISR, // 5.11 - Reserved
PIE_RESERVED_ISR, // 5.12 - Reserved
PIE_RESERVED_ISR, // 5.13 - Reserved
PIE_RESERVED_ISR, // 5.14 - Reserved
PIE_RESERVED_ISR, // 5.15 - Reserved
PIE_RESERVED_ISR, // 5.16 - Reserved
SPIC_RX_ISR, // 6.9 - *** Receive Interrupt
SPIC_TX_ISR, // 6.10 - *** Transmit Interrupt
PIE_RESERVED_ISR, // 6.11 - Reserved
PIE_RESERVED_ISR, // 6.12 - Reserved
PIE_RESERVED_ISR, // 6.13 - Reserved
PIE_RESERVED_ISR, // 6.14 - Reserved
PIE_RESERVED_ISR, // 6.15 - Reserved
PIE_RESERVED_ISR, // 6.16 - Reserved
PIE_RESERVED_ISR, // 7.9 - Reserved
PIE_RESERVED_ISR, // 7.10 - Reserved
PIE_RESERVED_ISR, // 7.11 - Reserved
PIE_RESERVED_ISR, // 7.12 - Reserved
PIE_RESERVED_ISR, // 7.13 - Reserved
PIE_RESERVED_ISR, // 7.14 - Reserved
PIE_RESERVED_ISR, // 7.15 - Reserved
PIE_RESERVED_ISR, // 7.16 - Reserved
PIE_RESERVED_ISR, // 8.9 - Reserved
PIE_RESERVED_ISR, // 8.10 - Reserved
PIE_RESERVED_ISR, // 8.11 - Reserved
PIE_RESERVED_ISR, // 8.12 - Reserved
PIE_RESERVED_ISR, // 8.13 - Reserved
PIE_RESERVED_ISR, // 8.14 - Reserved
#ifdef CPU1
UPPA_ISR, // 8.15 - uPPA Interrupt
PIE_RESERVED_ISR, // 8.16 - Reserved
#elif defined(CPU2)
PIE_RESERVED_ISR, // 8.15 - Reserved
PIE_RESERVED_ISR, // 8.16 - Reserved
#endif
PIE_RESERVED_ISR, // 9.9 - Reserved
PIE_RESERVED_ISR, // 9.10 - Reserved
PIE_RESERVED_ISR, // 9.11 - Reserved
PIE_RESERVED_ISR, // 9.12 - Reserved
PIE_RESERVED_ISR, // 9.13 - Reserved
PIE_RESERVED_ISR, // 9.14 - Reserved
#ifdef CPU1
USBA_ISR, // 9.15 - USBA Interrupt
#elif defined(CPU2)
PIE_RESERVED_ISR, // 9.15 - Reserved
#endif
PIE_RESERVED_ISR, // 9.16 - Reserved
ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt
ADCC2_ISR, // 10.10 - ADCC Interrupt 2
ADCC3_ISR, // 10.11 - ADCC Interrupt 3
ADCC4_ISR, // 10.12 - ADCC Interrupt 4
ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt
ADCD2_ISR, // 10.14 - ADCD Interrupt 2
ADCD3_ISR, // 10.15 - ADCD Interrupt 3
ADCD4_ISR, // 10.16 - ADCD Interrupt 4
PIE_RESERVED_ISR, // 11.9 - Reserved
PIE_RESERVED_ISR, // 11.10 - Reserved
PIE_RESERVED_ISR, // 11.11 - Reserved
PIE_RESERVED_ISR, // 11.12 - Reserved
PIE_RESERVED_ISR, // 11.13 - Reserved
PIE_RESERVED_ISR, // 11.14 - Reserved
PIE_RESERVED_ISR, // 11.15 - Reserved
PIE_RESERVED_ISR, // 11.16 - Reserved
EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt
RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt
FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt
RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt
SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt
AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt
CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt
CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt
};
//
// InitPieVectTable - This function initializes the PIE vector table to a
// known state and must be executed after boot time.
//
void InitPieVectTable(void)
{
Uint16 i;
Uint32 *Source = (void *) &PieVectTableInit;
Uint32 *Dest = (void *) &PieVectTable;
//
// Do not write over first 3 32-bit locations (these locations are
// initialized by Boot ROM with boot variables)
//
Source = Source + 3;
Dest = Dest + 3;
EALLOW;
for(i = 0; i < 221; i++)
{
*Dest++ = *Source++;
}
EDIS;
//
// Enable the PIE Vector Table
//
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
}
void EPWM_initEpwm(void)
{
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Turn off the EPWM clock
EPwm1Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC on up-count
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.CMPA.bit.CMPA = 2000; // Set compare A value to 2000
// counts
EPwm1Regs.TBPRD = 4000; // Set period to 4000 counts
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // freeze counter
EPwm1Regs.ETSEL.bit.SOCAEN = 1; //enable SOCA
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm2Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
EPwm2Regs.CMPA.bit.CMPA = 2048; // Set compare A value to 10000
// counts
EPwm2Regs.TBPRD = 4096; // Set period to 20000 counts
EPwm2Regs.TBCTL.bit.CTRMODE = 0; // freeze counter
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Clear PWM1A on Zero
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Clear PWM2A on Zero
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR;
GpioCtrlRegs.GPAMUX1.bit.GPIO2=1;
EDIS;
}
void ADC_initAdcA(void)
{
uint16_t i;
EALLOW;
//
//write configurations
//
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
//
//Set pulse positions to late
//
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//
//power up the ADC
//
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
//
//delay for > 1ms to allow ADC time to power up
//
for(i = 0; i < 1000; i++)
{
asm(" RPT#255 || NOP");
}
//
//Select the channels to convert and end of conversion flag ADCA
//
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert pin A0
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 99; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5; //trigger on ePWM1 SOCA/C
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; //end of SOC0 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
EDIS;
}
void CLA_configClaMemory(void)
{
//extern uint32_t Cla1funcsRunStart, Cla1funcsLoadStart, Cla1funcsLoadSize;
EALLOW;
#ifdef _FLASH
//
// Copy over code from FLASH to RAM
//
memcpy((uint32_t *)&Cla1funcsRunStart, (uint32_t *)&Cla1funcsLoadStart,
(uint32_t)&Cla1funcsLoadSize);
#endif //_FLASH
//
// Initialize and wait for CLA1ToCPUMsgRAM
//
MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1){};
//
// Initialize and wait for CPUToCLA1MsgRAM
//
MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1){};
//
// Select LS5RAM to be the programming space for the CLA
// First configure the CLA to be the master for LS5 and then
// set the space to be a program block
//
MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;
MemCfgRegs.LSxMSEL.bit.MSEL_LS4=1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;
//MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;
EDIS;
}
void main()
{printf("Him");
/* initialise system */
InitSysCtrl(); // [F2806x_SysCtrl.c]
DINT; // disable interrupts
IER = 0x0000;
IFR = 0x0000;
InitPieCtrl(); // initialise PIE control registers [F2806x_PieCtrl.c]
InitPieVectTable(); // initialise PIE vector table [F2806x_PieVect.c]
EALLOW;
PieVectTable.ADCA1_INT = &control_Isr;
EDIS;
/* initialise PI controller */
pi1.Kp = 5.5f;
pi1.Ki = 0.015f;
pi1.i10 = 0.0f;
pi1.i6 = 1.0f;
pi1.Umax = 10.2f;
pi1.Umin = -10.2f;
CLA_configClaMemory();
/* compute CLA task vectors */
EALLOW;
Cla1Regs.MVECT1 = (Uint16)((Uint32)&Cla1Task1);
Cla1Regs.MVECT2 = (Uint16)((Uint32)&Cla1Task2);
//Cla1Regs.MVECT3 = (Uint16)((Uint32)&Cla1Task3);
Cla1Regs.MVECT4 = (Uint16)((Uint32)&Cla1Task4);
Cla1Regs.MVECT5 = (Uint16)((Uint32)&Cla1Task5);
Cla1Regs.MVECT6 = (Uint16)((Uint32)&Cla1Task6);
Cla1Regs.MVECT7 = (Uint16)((Uint32)&Cla1Task7);
Cla1Regs.MVECT8 = (Uint16)((Uint32)&Cla1Task8);
Cla1Regs.MVECT3 = (Uint16)((Uint32)&Cla1Task3 -(Uint32)&Cla1Prog_Start);
/* CLA task triggers */
/* Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = CLA_INT1_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT2SEL = CLA_INT2_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT3SEL = CLA_INT3_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT4SEL = CLA_INT4_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT5SEL = CLA_INT5_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT6SEL = CLA_INT6_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT7SEL = CLA_INT7_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT8SEL = CLA_INT8_NONE;*/
Cla1Regs.MIER.all = 0x00FF;
/* Switch the CLA program space to the CLA and enable software forcing
* Also switch over CLA data ram 0,1 and 2
* CAUTION: The RAMxCPUE bits can only be enabled by writing to the register
* and not the individual bit field. Furthermore, the status of these bitfields
* is not reflected in either the watch or register views - they always read as
* zeros. This is a known bug and the user is advised to test CPU accessibilty
* first before proceeding
*/
// Cla1Regs.MMEMCFG.all = CLA_PROG_ENABLE|CLARAM0_ENABLE|CLARAM1_ENABLE|CLARAM2_ENABLE|CLA_RAM1CPUE;
Cla1Regs.MCTL.bit.IACKE = 1;
EDIS;
/* configure ePWM1 */
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC=1;
EDIS;
EPWM_initEpwm();
ADC_initAdcA();
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
/* configure ADC */
// [F2806x_Adc.c]
/* configure GPIO */
//InitGpio(); // [F2806x_Gpio.c]
EALLOW;
/* CLA setup */
Cla1Regs.MIER.bit.INT3 = 1;
// Cla1Regs.MIER.bit.INT8 = 1;
//Cla1ForceTask8andWait();
/* enable interrupts */
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // enable PIE INT 1.1 (ADCINT1) - [adcisr]
IER |= M_INT1; // enable CPU Interrupt 1 (TINT0)
EINT; // enable global interrupt mask
EDIS;
printf("%d",rk);
/* idle loop */
while(1)
{
IdleLoopCount++;
}
}
/* control ISR: triggered by ADC EOC */
interrupt void control_Isr(void)
{
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
// read ADC channel
yk = ((float) AdcaResultRegs.ADCRESULT0 - 2048.0f) / 2047.0f;
// trigger PI controller on CLA
EALLOW;
Cla1ForceTask3andWait();
// write u(k) to PWM
Duty = (uk / 2.0f + 0.5f) * (float) EPwm1Regs.TBPRD;
EPwm2Regs.CMPA.bit.CMPA = (Uint16) Duty;
if(uk==5.0f)
{EALLOW;
GpioCtrlRegs.GPAMUX1.all=0;
GpioCtrlRegs.GPADIR.bit.GPIO13=1;
EDIS;
GpioDataRegs.GPACLEAR.bit.GPIO13=1;
}
IsrCount++;
}
/* end of file */
This is the cmd file i am using
// The user must define CLA_C in the project linker settings if using the
// CLA C compiler
// Project Properties -> C2000 Linker -> Advanced Options -> Command File
// Preprocessing -> --define
#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C
_Cla1Prog_Start = _Cla1funcsRunStart;
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002
RAMM0 : origin = 0x000122, length = 0x0002DE
RAMD0 : origin = 0x00B000, length = 0x000800
RAMD1 : origin = 0x00B800, length = 0x000800
/*RAMLS4 : origin = 0x00A000, length = 0x000800*/
/*RAMLS5 : origin = 0x00A800, length = 0x000800*/
RAMLS4_LS5 : origin = 0x00A000, length = 0x001000
RESET : origin = 0x3FFFC0, length = 0x000002
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */
RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0
.text : >> RAMD0|RAMD1|RAMLS4_LS5, PAGE = 0
.cinit : > RAMM0, PAGE = 0
.pinit : > RAMM0, PAGE = 0
.switch : > RAMM0, PAGE = 0
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1
.stack : > RAMM1, PAGE = 1
.ebss : > RAMLS2, PAGE = 1
.econst : > RAMLS3, PAGE = 1
.esysmem : > RAMLS3, PAGE = 1
Filter_RegsFile : > RAMGS0, PAGE = 1
/* CLA specific sections */
Cla1Prog : > RAMLS4_LS5,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
LOAD_SIZE(_Cla1funcsLoadSize),
RUN_START(_Cla1funcsRunStart),
PAGE = 0
CLADataLS0 : > RAMLS0, PAGE=1
Cla1DataRam1 : > RAMLS1, PAGE=1
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
/* The following section definition are for SDFM examples */
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} > RAMM0, PAGE = 0
#else
ramfuncs : > RAMM0 PAGE = 0
#endif
#endif
#ifdef CLA_C
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS1, PAGE = 1
.scratchpad : > RAMLS1, PAGE = 1
.bss_cla : > RAMLS1, PAGE = 1
.const_cla : > RAMLS1, PAGE = 1
#endif //CLA_C
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
