Hi,
I have a strange issue, that I am sure is just code, but really could use some help figuring it out.
I have Timer0 configured to generate 10 ms interrupts. I'm not doing anything too heavy in the interrupt, and upon leaving the interrupt I'm clearing the Timer0 interrupt flag and also doing a PIEACK to PIE Group1.
I have SCIB setup in FIFO mode, and I have RxFIFO Int enabled. In the FIFO routine I check the error status, queue up any data and upon leaving I clear RxFIFO Overflow, RxFIFO Int and PIEACK to PIE Group9.
Both of these systems work well in separate verification projects, but when joined together I see some issues.
I loose Timer 0 Interrupts while sending data to the SCIB UART. If I send a small amount (~8 bytes) no worries with T0. If I send a large amount at full speed I loose Timer0 somewhere in between.
Maybe I'm not too familiar with the interrupt functionality, but from the register window, when the error occurs, I see the Timer0 IE and IF bits set, I can see PIEER1 and PIEIFR1 bit 6 set (Timer0) but at the same time I can see PIEACK bit 1 set, and its not being cleared.
My understanding is that writing a 1 to PIEACK.x should clear it.
Any suggestions?
Thanks.
Stomp!.