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CCS/TMS320F28335: Clearing existing SOCA event

rga88
Prodigy 40 points
Part Number: TMS320F28335


Tool/software: Code Composer Studio

Hello,

I'm using DMA only triggered by SOCA of a PWM submodule.

PWM and control task is not synchronized due to switching frequency is variable.

In a certain moment of the control task, I want to disable DMA, move some data with the CPU and reenable DMA. When I reenable the DMA I must be sure that DMA operation occurs synchronized with SOCA event. I do not what trigger DMA if SOCA event was latched.

How can I erase existing SOCA events before enable SOCA (SOCAEN=1;)?

Thank you

Kind Regards

  • 0
    TI__Mastermind 42195 points

    rga88,

    Are you generating the SOCA using the Event-Trigger sub-module? Take a look at the ePWM Reference Guide, it describes the function of the Event-Trigger sub-module. Figure 44 "Event-Trigger Interrupt Generator" should be helpful.

    • If an SOCA event is set, you can clear that using ETCLR[INT].
    • Depending on how you have ETPS[INTPRD] configured the 2 bit counter may be in an unknown state, you can reset the counter by writing to ETPS[INTPRD].
    • Also be sure to check that flag selected by ETSEL[INTSEL] is cleared, as it could immediately trigger an interrupt as well.

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Prodigy 40 points
    Hello,

    We are generating a SOCA signal to trigger several DMA channels (Thanks to PERINTSEL=20 for example in Figure 2 and Table 1 of DMA SPRUFB8D document).
    I suppose that Fig 45 of ePWM document applies (not 44). Is this correct?
    To disable all DMA channels at (exactly) the same time, SOCA events must be disabled (SOCAEN=0 for example)
    If a SOCA event occurs during SOCAEN=0, 2-bit counter increments and its output is 1. ETCLR[SOCA]=1 clears the ETFLG[SOCA], but no the output of the 2-bit counter. Is this correct?

    We have First event configuration (ETPS[SOCAPRD]=1). Can I change ETPS[SOCAPRD] from 1 to 0 to make 2-bit counter output=0 and after data is moved by the CPU reenable SOCA events forcing ETPS[SOCAPRD]=1 again? Is this robust or maybe the 2-bit counter enters in an unknown state?

    We have ETSEL[SOCASEL]=4. PWM is not stopped (it is controlling a power stage and it must keep working), so events in SOCASEL multiplexer will come. Reading ETSEL[SOCASEL] description, I understand that I can not disable SOCAevent through SOCASEL bits due to only valid configurations are 1,2,4,5,6,7 but 0 and 3 must be avoided. Is this correct?

    To sumarize, what is the correct way to perform a disable of SOCA, being sure that the enable procedure of the SOCA discards previous events at the moment of the re-enable?

    Thank you,

    Kind regards.
  • 0 in reply to rga88
    TI__Mastermind 42195 points

    rga88,

    yes Figure 45 is specifically for "SOCA" trigger generation. 

    Correct it appears that the 2-bit counter would not be reset.

    The documentation states that writing to SOCAPRD will clear the two bit counter, so I think you can simply rewrite your configuration of SOCAPRD=1 to reset the counter, no need to write a 0 first. This is robust, but remember that as soon as the CTRU=CMPA event happens it will increment the counter.

    If you aren't using Up-down count mode, or one of the CMPx events then you could ensure that one of the events would not occur. For example if in upcount mode CTRD= CMPx will never occur. This would be one possible way to disable it using SOCASEL. 

    The correct way to disable SOCA is to use SOCAEN. When re-enabling you should first clear the 2 bit counter by writing to SOCAPRD since it will be in an unknown state. 

    Regards,
    Cody