TMS320F28335: Further information on McBSP interface

Hello
I have a customer looking to use the TMS320F28335 MCU in addition to FPGAs for a design. The FPGA requires a serial interface (MCU master, FPGA slave) to transfer 6 or so 16-bit words on a regular basis. 

Queries:

SPI (non preferred) 

1. My understanding from reading the associated SPI reference guide document is that whilst the MCU has a dedicated SPI function, it appears fairly basic allowing only single word transfers at a time which is likely to involve a degree of software overhead to ensure data coherency. The user guide downloaded from the web does mention a 16 word TX/RX FIFO but it’s not clear how much overhead this removes since documentation still mentions software loading/unloading of SCITXBUF/SCIRXBUF in a timely fashion to ensure data coherency. It appears that the FIFOs have been added as a later feature but that the documentation hasn’t been fully aligned to remove any ambiguity?  Please can you clarify the operation using the FIFOs. For example on transmit, will the SPI interface automatically transmit words between FIFO and SCITXBUF until the Tx FIFO is empty? On receive, will the SPI interface automatically transfer words from SCIRXBUF to the RX FIFO until the Rx FIFO is full?

McBSP (preferred)

1. We need more than 1 serial bus so use of the two McBSP channels appears to be a better option. Configuring this interface as an SPI interface again appears to have limitations in that only 1 word is transmitted at a time. Using the McBSP interface in true McBSP mode does allow multiple back to back words to be transmitted in a frame. Ideally, following FSX assertion (using one phase) in a single transfer, we wish for the master to transmit 6 or so 16-bit words to the slave whilst at the same time receiving 6 or so 16-bit words back from the slave i.e. simultaneous bi-directional data flow as can be achieved with an SPI interface using 4 wires. Is there a way of achieving this using a McBSP port configured as a 4-wire interface? Otherwise a separate TX and RX transfer (6 wires) will have to be adopted which will not be the most efficient solution. Please can you outline connectivity requirements and associated register settings to achieve this arrangement.

    

2. The same query relates to the McBSP FIFOs that was outlined above for the SPI function. Can the Tx FIFOs be loaded with the 6 or so words and the transfer then occur automatically with minimal software overhead? On completion, will the corresponding 6 or so words from the slave device be available in the MCU Rx FIFO for retrieval, again with minimal overhead?  

Looking forward to your assistance and responses soon

Regards
Bob Bacon