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CCS/TMS320F28035: nested interrupt priority

user5019379
Intellectual 370 points

Part Number: TMS320F28035

Tool/software: Code Composer Studio

hello sir/Madam,

there are 2 interrupts used in my project, one is the timer 0 which generate INT1 to CPU has a CPU priority 5.

the other one is EPWM_INT which generate INT4 to CPU has a CPU priority 7.

for some reason,  INTM is cleared during the timer0 ISR, and then i found that this ISR will be interrupted by ISR of EPWM_INT.

how that a ISR with lower priority could interrupt another one with  a higher priority? 

Can you tell me what's the problem here? thank you very much.

  • 0
    TI__Guru 61235 points

    user5019379,

    Priority only applies on C2000 devices when more than one interrupt is pending at exactly the same time.  In your case, once you get in an ISR, the processor has no idea it is in an interrupt routine.  Any enabled interrupt the occurs will interrupt the ISR.

    If you want to apply a priority to your nested interrupts, then manually adjust the PIEIERx and IER registers before clearing the INTM.  Only leave enabled the interrupts that you want to be able to interrupt you.

    Regards,

    David