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TMS320F28375D: Question about "EMIF : SDRAM Read Operation"

Shinji Ueda
Expert 5440 points
Part Number: TMS320F28375D
Other Parts Discussed in Thread: C2000WARE

Hi champs,

I have some questions about "EMIF SDRAM Read Operation".


TRM P.2608, 25.3.5.9 SDRAM Read Operation
In this Figure 25-6 s, there are eight data transfers. ". Figure 25-6 shows a burst size of eight."

1.Is this only support for 8 burst size transfer? 

2. When it needs only "D2", How does it do that?

3. Conversely, if it needs a lot of data(like a 16 or 32 data), how does it do that?

4.Is there any document about these use case?

Regards,

Shinji Ueda

  • 0
    TI__Guru** 116021 points

    Ueda-san,

    Burst transfers are not supported for SDRAM on this device. 

    We have following statement in device datasheet (section 5.8.9.2 Synchronous DRAM Support)



    So every access is single access. We are aware of the issue with timing diagram and it has been noted in our system to update in next release. Handling of 16bit and 32bit data is done inside hardware and transparent to user. If user reads 32bit data it'll return 32bit data and if 16 then 16bit data is returned.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Expert 5440 points
    Vivek-san,

    Thank you for your reply, and sorry for my late reply.

    TRM Figure 25-6. Timing Waveform for Basic SDRAM Read Operation
    This "D1", "D2", "D3", "D4"... are bit of data, not Data line(16 or 32 bit data), correct?

    I'm looking for "single access" software.
    Can I easily test with "EMIF1 module accessing 32bit SDRAM using memcpy_fast_far()" project on C2000ware ?
    Is there any other document that is easy to understand?


    Regards,
    Shinji Ueda
  • 0 in reply to Shinji Ueda
    TI__Guru 62975 points

    Shinji-san,

    The Dn refer to memory words on the parallel bus, not data bits.  You can refer to this EMIF Application Note for some background and usage information.

    Yes, you can test the EMIF behavior using writes if no memory is connected.

    -Tommy

  • 0 in reply to tlee
    TI__Expert 5440 points
    Tommy-san, Vivek-san,

    Thank you for your reply.
    I have a one more question.

    > TRM Figure 25-6. Timing Waveform for Basic SDRAM Read Operation
    > This "D1", "D2", "D3", "D4"... are bit of data, not Data line(16 or 32 bit data), correct?


    Could you please teach me the correct Timing Waveform when reading / writing one 32-bit data?
    Fig 25-6 "D1", "D2", "D3", "D4"... are not bits, I think that each of them is data.

    Regards,
    Shinji Ueda
  • 0 in reply to Shinji Ueda
    TI__Guru** 116021 points

    Shinji-san,

    The D1, D3, D3 are data and not the bits of same data but this waveform is for burst mode which is not supported on this device. We already have action to correct this diagram in next release. Basically each of these access will not be back-to-back instead there will be CAS latency between each data access.If you are doing 32bit data access on 16bit interface (external memory device is 16bit) then you'll see two back-to-back access of 16bit and next access will have cas latency.

    I would suggest to go through following app note to get the data throughput number for SDRAM access.

    Regards,

    Vivek Singh