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CCS/TIDM-1007: Spll_1ph_sogi library function

Ankit Shah17
Prodigy 80 points
Part Number: TIDM-1007
Other Parts Discussed in Thread: CONTROLSUITE, C2000WARE,

Tool/software: Code Composer Studio

Hello, 

I am using spll_1ph_sogi library function for my single phase pll. I am appling an input to it using function generator. 50Hz sine. 

When I check the spll1.sine output and compare it with the input i.e. spll1.u[0], it is 90deg phase shifted. Then I checked Orthogonal signal osg_u[0] i.e. Alpha component which is also 90deg phase shifted to my input. 

I have configured DACs to check both signals. 

Is there any mistake while checking the output?

  • 0
    TI__Genius 11955 points

    Both the sine and cosine components cannot be 90 deg phase shifted relative to the input. A detail documentation for this PLL module is available in the TI Controlsuite Solar library. Pls review this doc and validate your code. You can also send us your code and we will get back to you.

    Shamim

  • 0 in reply to Shamim Choudhury
    Prodigy 80 points

    Hi Shamim,

    Perhaps You have misunderstood my query.

    I have taken the library code for "spll_1ph_sogi.h" of TI from c2000Ware_DigitalPower_SDK_1_00_00_00 folder as below.

    C:\ti\c2000\C2000Ware_DigitalPower_SDK_1_00_00_00\libraries\spll

    This code is also used in TI Reference design of "pfc1ph3ilttpl" TIDM-1007 design as well. I am trying to measure the spll in this reference design. request you to please refer the same code for signals notations.

    I measured the output signal spll1.sine w.r.t. input signal spll1.u[0], The phase difference is 90deg.

    I measured the signal spll1.osg_u[0] (Alpha component of Orthogonal generated signals from 1ph sine input) w.r.t. input singal spll1.u[0], The phase difference is 90deg. 

    I measured the signal spll1.osg_qu[0] (Beta component of Orthogonal generated signals from 1ph sine input) w.r.t. input singal spll1.u[0], The phase difference is 180deg.

    For the measurement, I used DACs. DACa is configured for input signal and DACb is configured with output signals.

    Request you to please let me know if I made any mistakes in measurement or any update is there in code which I have not done.

  • 0 in reply to Ankit Shah17
    TI__Mastermind 43730 points
    Ankit,

    The SPLL module should work and show you exact phase synchronization between the input and the PLL output. Othwerwise the system will not work. We have tested and used this module on several TI Designs.

    1. You can look at the www.ti.com/.../sprabt3a.pdf where we show validation of exactly this, the matlab simulation file is also included in the app report.

    2. On the specific topic of what you are observing, it does not make sense to me.. I would suggest

    a. If you are using the same SW as for TIDM-1007, you can run incremental build level 1 and then observe on the datalogger

    you can update the dlog to be

    // check output voltage and inverter current meas.
    dVal1 = acSine;
    dVal2 = ac_vol_sensed);


    Can you provide datalogger graphs as we describe in the UG for this build level ??


    b. Additionally we also provide a software check, in build level 1 where if you select DC input we use a ramp gen output to test the module

    Also make sure you are comparing spll1.sine to the ac_vol_sensed

    Also make sure there is no hardware inversion in your sensing circuit etc..

    I believe if you provide 2.a, it can give us details or pointers to the issue at hand.
  • 0 in reply to Manish Bhardwaj
    Prodigy 80 points
    Hi Manish,
    I am using the reference design and made changes in below parameters:
    PFC_PWM_SWITCHING_FREQUENCY 200*1000
    CNTRL_ISR_FREQ_RATIO 2

    This two parameters are used for CONTROL_ISR_FREQUENCY calculation as below.
    (PFC_PWM_SWITCHING_FREQUENCY)/(CNTRL_ISR_FREQ_RATIO)

    and this is finally used for calculating the delta_t in SPLL_1PH_SOGI_coeff_calc using (1/CONTROL_ISR_FREQUENCY ).

    I guess this has an associative error for division and so the result changes.
    The desired value of delta_t is 10uSec, But this gives output as 2.5uSec.

    I changed the CONTROL_ISR_FREQUENCY as (PFC_PWM_SWITCHING_FREQUENCY/CNTRL_ISR_FREQ_RATIO) and I got the correct result( input and output are in sync).
  • 0 in reply to Ankit Shah17
    TI__Mastermind 43730 points
    BODMAS at play..

    OK i am glad its working,

    I have filed a bug to get this fixed in the next release.