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TMS320F280049: Valley Switching

Part Number: TMS320F280049

Hello,
is there any app note or description how the new valley swiching feature of PWM Type 4 can be implemented and how it works?
Is there any extra routing on PCB needed?

Regards, Holger

  • Hi HS WG,

    The valley switching implementation by using Type 4 PWM can be found in the document below under chapter "14.11.4.3 Valley Switching"
    www.ti.com/.../spruhm8g.pdf.
    This is the TRM of f2837x, however, it has type-4 PWM in it same as f28004x.

    This requires only an extra Vds sensing circuit for valley capture based on the ILPFC EVM. Thank you.

    Best regards,
    Chen
  • Dear Chen,

    trying to configure valley switching I can't find the right options for DCFCTL.EDGEMODE register.

    Could you detail the available options for this register?

    On SPRUHM8G page 1880 there is only this information.

    thanks,

    salicru.

  • Hi Salicru,

    The edgemode can be set according to the information below:

    default = 0
    EDGE_MODE = 0 --> low to high edge transitions for edge filter
    EDGE_MODE = 1 --> high to low edge transitions for edge filter
    EDGE_MODE = 2 --> both edge transitions for edge filter

    This bit can determine what kind of edge to be counted in the edge filter. Hope this helps.
    Thank you for your question.

    Best regards,
    Chen
  • Dear Chen,

    I have been trying to configure the valley switching for a F2837xD device and I do not get the expected results.
    I'm using a board manufactured on March 2017.
    Could it be that this option was not implemented on March 2017?
    I think that Valley Switching was not explained on the manual on those dates.

    thanks and BR,

    salicru.
  • Hi Salicru,

    From the hardware point of view, if you are using the 2 Phase Interleaved Boost PFC Base Board, you have to add an extra Vds sensing circuit for valley capture. I don't think the board you are using right now has this part implemented, however, it should not be very complicated. The device F2837xD can support valley switching once you add the Vds sensing circuit.
    For the software, we temporally have the instructions in the TRM of f2837x as I mentioned in the previous reply.

    We will release more updated S/W and H/W details about valley switching implementation in the near future. Thanks. Feel free to come back if you have more questions on this.

    Best regards,
    Chen
  • Dear Chen,

    I do not have any test board. I have our own developed control board.
    I'm trying to give a delay to a GPIO input to trigger a TZ signal to stop the PWM.

    As the valley switching detection can add a SW delay, I want to count 1 pulse, apply the desired SW delay, activate the TZ signal and stop PWM.
    After configuring the device as indicated in the manual I don't get the expected results.

    So, could it be that this option was applied on F28377D after march 2017? Is this why it was updated on the manual on December 2017?
    Should I buy a new F28377D to get this function available?
    Or maybe the march 2017 manufactured F28377D units have this option and I'm doing something wrong on the configuration?

    thanks in advance,

    Salicru.
  • Hi Salicru,

    Both F28377 and F28004x should be ok. The type-4 PWM is used for all F28377 and F28004x.

    according to the instruction below in TRM of f2837x:
    7. Configure and apply the captured delay (CNTVAL) to the edge filtered DCxEVTy signal. The CNTVAL
    value may be applied as is or applied in conjunction with a software programmed value (useful for
    offset adjustment) (SWVDELVAL) or only a fraction of the delay may be applied with or without
    SWVDELVAL. This is useful to correctly apply a delay corresponding to the valley point.
    (VCAPCTL[VDELAYDIV])

    You don't need to activate the trip zone to stop each PWM cycle. The SW delay will delay the DCEVT signal based on the SWVDELVAL you set and directly reset the time base counter. If you take a look at the time base module of PWM in page 1685, you will find there is a path between TBCTR and DCEVT. You need to enable the TBCTL[PHSEN] to make it happens. Thanks.

    Best regards,
    Chen