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TM4C1231H6PGE: Questions on SSI module within TM4C123

Richard Chen75
Intellectual 550 points

Part Number: TM4C1231H6PGE

Hi all, by reading the data sheet of TM4C123, I am not very clear on how the timing of SSI transmission works and wonder if anyone can clarify a few things here. I am using SSI1 as a SPI host, here is what I am not certain:

1) When will the transmission start? Is is true that the data will be transmitted out as long as the transmission FIFO is NOT empty and SSE bit in SSICR1 is set?

2) Does the transmit/receive logic within SSI module determine all SPI bus timing timing ? For example, when sending data out, it will drive the SSI1Fss pin to low to serve as the Chip Selecting, and enable the SSI1clk pin to send out clocks?

3) If 2) is true, when reading the data from the salve, how does transmit/receive logic know when the slave finishes the data sending so that it knows how long it should keep SSI1Fss as low?

Thanks

Richard

  • 0
    TI__Guru**** 191886 points

    Hi Richard,

    Richard Chen75 said:

    1) When will the transmission start? Is is true that the data will be transmitted out as long as the transmission FIFO is NOT empty and SSE bit in SSICR1 is set?

    Yes

    Richard Chen75 said:

    2) Does the transmit/receive logic within SSI module determine all SPI bus timing timing ? For example, when sending data out, it will drive the SSI1Fss pin to low to serve as the Chip Selecting, and enable the SSI1clk pin to send out clocks?

    Your understanding is correct.

    Richard Chen75 said:

    3) If 2) is true, when reading the data from the salve, how does transmit/receive logic know when the slave finishes the data sending so that it knows how long it should keep SSI1Fss as low?

    If you are the master then you control the SSI1Fss and the SSICLK. The master kernel knows how many clocks it needs to generate (based on the configured char length) to the slave and while in transmission it will keep the chip select low.  The slave will expect the SPI clock coming from the master and based on the agreed/configured char length the slave will send its data on its MISO pin. You can use the end-of-transmission interrupt to know the end of the last bit completed. 

  • 0 in reply to Charles Tsai
    Intellectual 550 points
    Charles, thank you so much for the quick response! For question 3), yes I am using SSI1 as the SPI master, in case of reading, the following data will be transmitted to the slave over MOSI: 1) Command Byte 2) Register Index. After receiving these two bytes, the slave is supposed to send out the register value as the reply via MISO line, what I don't understand is how Transmit/Receive logic knows how many bytes the slave will be sending so that it can keep driving the SSIsFss low as well as keep SSI1Clk alive to guarantee that the replied data will be transmitted to the master successfully? Is there an interface that the software can use to configure the SSI1 module on this regard?

    Thanks again,
    Richard
  • 0 in reply to Richard Chen75
    Intellectual 550 points
    Or should I transmit same amount of dummy data as what to be expected from the slave to have the SSI1 module hold SSI1Fss and SSI1Clk valid?

    Thanks
    Richard
  • 0 in reply to Richard Chen75
    TI__Guru**** 191886 points
    Hi Richard,
    Sorry that i missed replying you. Are you still looking for answers? If you are the master then you know how many bytes you want to read. If you need to read N bytes then your master need to provide clocks for the N bytes. The slave is a reactive device. If the slave is in some type of burst mode then it should keep reply the data via the MISO as long as clocks and chip select are active.
  • 0 in reply to Charles Tsai
    Intellectual 550 points

    Thank you Charles, yes, I have had my code working in the way mentioned in your reply.

    Regards,

    Richard