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TMS320F28375S: ADC power supply pins

Aaron Spaete
Expert 4597 points
Part Number: TMS320F28375S


Team,

My customer has the following question:

I have another question on the processor’s A/D, this time about the power supply pins. The datasheet says it would like VDDA to be between 3.14V and 3.47V. My 3.3V supply could possibly dip below this briefly (and possibly overshoot) when we transmit data on a MIL-STD-1553 bus. My 3.3VDDA is supplied from a ‘filtered’ 3.3VD (supply to VDDIO and such as well as everything else in the system). VREFHI is 2.5V. Do you know if these transients could affect the A/D conversions? Do you know if supplying VDDA with 2.8V or 3.0V would have any detrimental effects? I’m thinking of replacing the LC filter with an LDO with high PSRR/line regulation, but would like to supply it from the 3.3VD.

Regards,

Aaron

  • 0
    TI__Guru 60865 points
    Hi Aaron,

    Supplying the VDDA with 3.0V or 2.8V will certainly create ADC performance issues. There is also a requirement that VDDIO and VDDA be within 0.3V of each other at all times (see note 1 here: www.ti.com/.../recommended-operating-conditions-tsprs880-83120041015401

    Transients above/below the operating range are also obviously a problem. The ADC itself does have some reasonable amount of PSRR from transients on the VDDA rail (this is specified in the datasheet in the ADC electrical characteristics section), although this has only been characterized with transients inside the operating range.

    Probably you need to limit the transients on the 3.3V rail to within +/-5% or use an LDO from an input source > 3.3V.
  • 0 in reply to Devin Cottier
    TI__Expert 4597 points
    Devin,

    Thanks for the quick reply. They do have a 6V rail that may be available; it only supplies up to 60 mA, so will have to take a closer look at all of its loads if they were to add the VDDA to this. As far as the “within 0.3V of each other at all times”, does this include power-up and power-down? If the 3VDDA came up around 10-20 ms later, but then stayed within 0.3V after that, is there still risk of damage?

    Regards,
    Aaron
  • 0 in reply to Aaron Spaete
    TI__Guru 60865 points
    Hi Aaron,

    Yeah, that also includes during power-sequencing. If they aren't maintained within 0.3V, then current will start to flow through parasitic paths, potentially causing damage. We mostly expect VDDIO, VDDA, and VDD3VFL to come from the same source.

    VDDIO also requires 3.3V +/-5%, so I think you still have a problem there too.