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CCS/TMS320F28379D: PWM Frequency always half

Part Number: TMS320F28379D
Other Parts Discussed in Thread: LAUNCHXL-F28379D, CONTROLSUITE

Tool/software: Code Composer Studio

I'm testing the LAUNCHXL-F28379D by using the example projects provided by texas instruments, the problem is that the  PWM frequency is always half of the examples.. I have tried many examples in the controlsuite and also the examples provided in "http://processors.wiki.ti.com/index.php/C2000_One-Day_Workshop". The last one I tried in the the workshop "http://processors.wiki.ti.com/index.php/C2000_One-Day_Workshop" with the project named "Lab3_cpu01" was supposed to present a 2kHz PWM output... However, when measuring with the oscilloscope the output frequency is 1kHz... 

I just bought this board and I'm wondering if the board is somehow deffective... 

Can anyone please help me?

  • Hi,

    Two points to note -

    1. On this device PWM runs 1/2 of SYSCLK frq unlike earlier devices where PWM used to run at SYSCLK.
    2. On launchpad the external crystal is 10MHz instead of 20MHz hence the SYSCLK frq may be 1/2 of what example is expecting. In that case you need to change the PLL multiplier.

    Regards,

    Vivek Singh

  • Guilherme,

    In your project Properties, please check the configuration of the predefined symbols. Under “C2000 Compiler” select “Advanced Options” and then “Predefined Symbols”. In the predefined name box (“Pre-define NAME”) see if the “Enter Value” window has CPU1 and _LAUNCHXL_F28379D (note leading underscore). These names are used in the project to conditionally include the peripheral register header files code specific to CPU1 and the LaunchPad.

    Specifically, this does a software correction for the external crystal that is used on the F28379D LaunchPad:

    #ifdef _LAUNCHXL_F28379D
    InitSysPll(XTAL_OSC,IMULT_40,FMULT_0,PLLCLK_BY_2);
    #else
    InitSysPll(XTAL_OSC, IMULT_20, FMULT_0, PLLCLK_BY_2);

    Also, please try loading the solution for Lab 7 in the following workshop:

    processors.wiki.ti.com/.../C2000_Multi-Day_Workshop

    In this workshop, the internal 10 MHz oscillator is used, so no correction is needed. Run this lab exercise and measure the PWM waveform. It should be 2 kHz.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • Ken,

    I configured the "Predefined Symbols" asyou mentioned before... I also noticed that when the command "InitSysPll(XTAL_OSC, IMULT_20, FMULT_0, PLLCLK_BY_2);" is used the PWM frequency is 1/4 from expected, while when the command "InitSysPll(XTAL_OSC, IMULT_40, FMULT_0, PLLCLK_BY_2);" is used the PWM frequency is 1/2 from the expected value.. 

    I'm trying to run the Lab7 that you mentioned but it seems that there are many empty configurations in the PWM initialization code...

  • Vivek, as Ken mentioned, the "F2837xD_SysCtrl.c", which is included in the examples should be able to correct this problem since the command InitSysPll(XTAL_OSC,IMULT_40,FMULT_0,PLLCLK_BY_2); is equal to 200Mhz = 10Mhz (XTAL_OSC)* [40 (IMULT_40)+ 0 (FMULT_0)]/ 2 (PLLCLK_BY_2)
    Right?


    #ifdef _LAUNCHXL_F28379D
    InitSysPll(XTAL_OSC,IMULT_40,FMULT_0,PLLCLK_BY_2);
    #else
    InitSysPll(XTAL_OSC, IMULT_20, FMULT_0, PLLCLK_BY_2);
  • Guilherme,

    From you post:

    I'm trying to run the Lab7 that you mentioned but it seems that there are many empty configurations in the PWM initialization code...

    That is why I told you to run the solution code. You will find this in the solutions folder.

    - Ken
  • Ok!

    I found the problem.. 

    the ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV must be zero, otherwise the output frequency will be divided by 2. 

    Thank you Ken! 

  • Hi,

    Please note that max frq supported for PWM on this device is 100MHz (please refer Table 5-12. Internal Clock Frequencies of device maual) so if you are running the SYSCLK at 200MHz then you have to set this divider to divide by 2.

    Regards,

    Vivek Singh
  • Guilherme,

    I am glad that you found the problem. Just for reference, from my workshop lab file:

    // Configure the prescaler to the ePWM modules. Max ePWM input clock is 100 MHz.
    ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 1; // EPWMCLK divider from PLLSYSCLK. 0=/1, 1=/2

    We are running the device at 200 MHz and the above structure is set to 1 for this reason. Your setting will depend on you PLLSYSCLK value (see module 5).

    - Ken
  • Thanks for your attention Ken!

    Guilherme.