Part Number: TMS320F280049
Other Parts Discussed in Thread: C2000WARE
Tool/software: Code Composer Studio
Hi everyone,
I have a custom board for the TMS320F280049 microcontroller. I am using the example projects with the C200ware, which supports the new microcontroller. It looks like the header files are intended to be used with a development board or something. This is another thread I posted regarding my design https://e2e.ti.com/support/microcontrollers/c2000/f/171/p/673208/2478927#2478927.
I have a difficulty in running my code from the FLASH, however, it runs ok from the RAM. I have changed the variable ".TI.ramfunc" to "ramfuncs" to match all the other microcontroller families.
I have included my code in this post.
/ Included Files
//
#include "F28x_Project.h"
//
// Defines
//
#define DEVICE_GPIO_PIN_LED1 12
uint32_t NewVar=10;
//
// Main
//
void main(void)
{
//
memcpy(&RamfuncsRunStart,&RamfuncsLoadStart,&RamfuncsLoadEnd - &RamfuncsLoadStart);
// Initialize device clock and peripherals
//
InitSysCtrl(); This function was internally changed to use an internal oscillator " InitSysPll(INT_OSC2,19,1,1);"
//
// Initialize GPIO and configure the GPIO pin as a push-pull output
//
InitGpio();
GPIO_SetupPinMux(DEVICE_GPIO_PIN_LED1, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(DEVICE_GPIO_PIN_LED1, GPIO_OUTPUT, GPIO_PUSHPULL);
//
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
//
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
InitPieVectTable();
NewVar = 12;
//
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
//
EINT;
ERTM;
NewVar = 13;
//
// Loop Forever
//
for(;;)
{
//
// Turn on LED
//
GPIO_WritePin(DEVICE_GPIO_PIN_LED1, 0);
//
// Delay for a bit.
//
DELAY_US(1000000);
//
// Turn off LED
//
GPIO_WritePin(DEVICE_GPIO_PIN_LED1, 1);
NewVar = 15;
//
// Delay for a bit.
//
DELAY_US(1000000);
}
}
//
// End of File
//
void InitSysCtrl(void)
{
//
// Disable the watchdog
//
DisableDog();
#ifdef _FLASH
//
// Copy time critical code and Flash setup code to RAM
// This includes the following functions: InitFlash();
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart
// symbols are created by the linker. Refer to the device .cmd file.
//
//memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
memcpy(&RamfuncsRunStart,&RamfuncsLoadStart,&RamfuncsLoadEnd - &RamfuncsLoadStart);
#endif
//
// PLLSYSCLK = (XTAL_OSC) * (IMULT + FMULT) / (PLLSYSCLKDIV)
//
//InitSysPll(XTAL_OSC,IMULT_10,FMULT_0,PLLCLK_BY_2);
//InitSysPll(INT_OSC2,IMULT_19,FMULT_0pt25,PLLCLK_BY_2);
InitSysPll(INT_OSC2,19,1,1);
//
// Call Flash Initialization to setup flash waitstates
// This function must reside in RAM
//
InitFlash();
//
// Turn on all peripherals
//
InitPeripheralClocks();
}
//
// InitFlash - This function initializes the Flash Control registers
// CAUTION
// This function MUST be executed out of RAM. Executing it
// out of OTP/Flash will yield unpredictable results
//
#ifdef __cplusplus
#pragma CODE_SECTION("ramfuncs");
#endif
void InitFlash(void)
{
EALLOW;
//
// At reset bank and pump are in sleep
// A Flash access will power up the bank and pump automatically
// After a Flash access, bank and pump go to low power mode (configurable
// in FBFALLBACK/FPAC1 registers)- if there is no further access to flash
// Power up Flash bank and pump and this also sets the fall back mode of
// flash and pump as active
//
Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1;
Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3;
Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR1 = 0x3;
//
// Disable Cache and prefetch mechanism before changing wait states
//
Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0;
Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0;
//
// Set waitstates according to frequency
// CAUTION
// Minimum waitstates required for the flash operating
// at a given CPU rate must be characterized by TI.
// Refer to the datasheet for the latest information.
//
#if CPU_FRQ_100MHZ
if((ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0x0) ||
(ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0x2) ||
(ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0x3))
{
Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x5;
}
else
{
Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x4;
}
#endif
//
// Enable Cache and prefetch mechanism to improve performance
// of code executed from Flash.
//
Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1;
Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1;
//
// At reset, ECC is enabled. If it is disabled by application software
// and if application again wants to enable ECC
//
Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA;
EDIS;
//
// Force a pipeline flush to ensure that the write to
// the last register configured occurs before returning.
//
__asm(" RPT #7 || NOP");
}
//
// FlashOff - This function powers down the flash
// CAUTION
// This function MUST be executed out of RAM. Executing it
// out of OTP/Flash will yield unpredictable results.
// Note: a flash access after the flash pump and banks are powered down will
// wake the pump and bank
//
#ifdef __cplusplus
#pragma CODE_SECTION("ramfuncs");
#endif
void FlashOff(void)
{
EALLOW;
//
// Configure the fallback power mode as sleep
//
Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0;
Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR1 = 0;
//
// Configure the fallback power mode as sleep
//
Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0;
EDIS;
}
