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TMS320F28379D: CLA and absolute encoder in the fast current loop example codes

Wayne Huang
Genius 16675 points
Part Number: TMS320F28379D


Dear Champs,

I am asking this for our customers.

1) CLA in FCL

How is CLA used in our FCL?

Can you explain why CLA can accelerate the computation?

(We cannot reason because even there are two cores (C28x/CLA), it seems CLA still needs to wait for C28x or C28x waits for CLA for the results.)

In our FCL library, it seems CLA codes are not open?

2) In FCL, QEP is used.

If absolute encoder (by CLB) is used rather than QEP, will the latency dominated by the absolute encoder?

We notice in FCL v2, there is encoder interface for Endat, Biss, and resolver.

Can Tamagawa be used as well?

Wayne

  • 0
    TI__Mastermind 27240 points

    Hello,

    CLA has minimal latency than CPU to respond to an interrupt. Therefore, it can finish QEP computation earlier than if a CPU were used. 

    In FCL v2, you may see inits for ENDAT/BiSS, because the base code is derived from IDDK v2 example. But only QEP is used in our FCL releases so far. If any abs encoder is used, then this will increase latency and work arounds may be needed.

    Tamagawa can also be used, but we have not released the code yet.

  • 0 in reply to Ramesh Ramamoorthy
    TI__Genius 16675 points

    Ramesh,

    Let me clarify.

    1) CLA usage with C28x

    CLA is only used for QEP computation, but it's not used for other computations like PI/complex controllers.

    After CLA computes QEP, it still needs to interrupt C28x to get the QEP result.

    Is my understanding right?

    2) From the above, if abs encoder is used, we may not need to use CLA as existing abs encoder like Endat, Biss-C, Tamagawa are done by C28x and CLB. But latency is increased, and we should have workaround for that.

    Is my understanding correct?

    Wayne Huang

  • 0 in reply to Wayne Huang
    TI__Mastermind 27240 points

    1. Right. But CLA also does one of the current regulators besides the QEP. Your observation about the latency between CLA task completion and CPU acceptance of the CLA output is true but is kept as minimal as we can.

    2. True, it may be possible to link CLB with CLA. But, in any case, a work around may be needed because of the residual latency of serial transmission of encoder data.

  • 0 in reply to Ramesh Ramamoorthy
    TI__Genius 16675 points

    Ramesh,

    Thank you for your information.

    Wayne