• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 81 subscribers
  • Views 712 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

F28M35H52C: Behaviour of EPI as GPMODE reading data by C28

Guanglei
Prodigy 100 points
Part Number: F28M35H52C


Hi, I tried to read data from FPGA through EPI by C28 as fast as it could. As discussed in other threads, the fastest cylce read by EPI could be two EPI clocks in GPIO MODE. So the EPI is configured as following:

EPI clock = 75MHz; MODE = GPMODE; READ2CYCLE = 1; ASIZE =12; DSIZE =16;

C28 clock =150MHz;

The RTW registers remains as default.

When the M3 was initialized, it halted. I checked the behaviour of EPI in C28 using the assembly codes:

....

movl xar1, #_getBuff ; read buffer

movl xar0, #_EPI_ADDR ; 0x30 0000

L1: .loop 16

mov al,*XAR0

mov *XAR1, al

.endloop

rpt #255

|| nop

bf L1, unc

......

Howerver, one reading cylce are almost 10 C28 cycles, equal to 5 EPI Clocks, more than the expected. And I checked the RD (EPI0S29) and CLOCK (EPI0S31) pin using the oscilloscope. There were almost 4 EPI clocks between the RD signals. The question is: Is this behaviour normal? Or, is there any incorrect configuration described above?

  • 0
    TI__Guru 62975 points

    Guanglei,

    What is your frequency for the M3 Master Subsystem?  Note that EPI is clocked from the Master clock:

    -Tommy

  • 0 in reply to tlee
    Prodigy 100 points
    Hi, Tommy.

    I've noticed that the clock source of EPI is from M3SSCLOCK, which is configured the same as EPI CLOCK --75MHz. As mentioned above, when observed, the actual reading cycles from C28 are much more than 2 EPI clock (given in the technical reference). Dose it make sense, or are there any unproper usage in my configuration?

    Regards,
    Guanglei
  • 0 in reply to Guanglei
    TI__Guru 62975 points
    Guanglei,

    In order to maximize EPI read efficiently, you will need to use non-blocking reads so that the local NBRFIFO is used. Otherwise, the C28 read transactions will be treated as discrete operations, and each transaction will suffer from internal bus latencies.

    If you have a large block of data to transfer, the uDMA will be the most efficient means of doing so. You can use the IPC to send a message from C28 to M3 so that the M3 can initiate the uDMA transfer to shared RAM.

    -Tommy
  • 0 in reply to tlee
    Prodigy 100 points

    Tommy,

    The configuration registers of EPI could only be written by the master subsystem. Could it be possible that EPI is configured by M3 then reading is triggered with EPIRPSTD0 written by C28?

    regards,

  • 0 in reply to Guanglei
    TI__Guru 62975 points
    Guanglei,

    As you have stated, only the Master Subsystem can access the EPI configuration registers so you would need to program the M3 to perform such tasks when requested by the C28x. The most direct means of supporting the inter-processor handshaking is through the IPC mailboxes.

    From the C28x perspective, you can write a CtoM message to ask the M3 to perform a non-blocking read and then wait for the M3 to respond. The M3 can then use either the uDMA or directly copy FIFO read data to shared RAM and then send a MtoC message indicating that the data is ready.

    -Tommy
  • 0 in reply to tlee
    Prodigy 100 points

    Thanks!