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TMS320F28377D: spi high speed

z.z
Prodigy 200 points

Part Number: TMS320F28377D

Hi,

F28377-SPI has high speed mode activated by SpiaRegs.***.bit.HS_MODE,If I do not enable high speed mode, configure the low speed clock to 200M with ClkCfgRegs.LOSPCP.bit.LSPCLKDIV =0.

Can I configure SPIBRR to 4 or 9 for 40M or 20M, or must I enable High Speed Mode? When should the high speed mode be used, what is the highest clock frequency in high speed mode, 200M?

thank you！

  • 0
    Guru 30330 points
    Hello z.z,

    Using the HS_MODE of the SPI allow you to achieve the timings as specified in the Datasheet : www.ti.com/.../high-speed-master-mode-timings-sprs945-hispeed-master-section .

    The Highest Frequency possible on the F2837x devices when operating at 200 MHz SYSCLK is 50 MHz SPICLK as there is a minimum divider of LSPCLK/4 always in the SPI (remember that LSPCLK can be set equal to SYSCLK).

    I can only give you guidance here on when or when not to use HS_MODE. It is determined by the combination of external device timing requirements with the switching characteristics of the F2837x device as well as the switching characteristics of the external device with the timing requirements of the F2837x. i.e. for a 50MHz SPICLK, when attempting full duplex communication, there is only 20 ns available to send the first edge of the clock and the data, have the slave detect that edge, latch data, transmit the Slave data out, and then for the master to detect and latch the slave data. This is the longest path of the SPI. the HS_MODE adjusts the timings to allow this to work. Please analyze the timings and let me know if you have additional questions.

    Thanks,
    Mark