TMS320F28379D: Advise at sharing variables between the 2 cores

Part Number: TMS320F28379D

Hello,

I'm working with the TMS320F28379D and I need some advise at sharing variables between the two cores.

First some details of my application:

• Both cores are running under SYS/BIOS;
• Both CLAs are enabled;
• Each core run a real time critical application and some other tasks;
• I have 3 Finite State Machines on each core;
  • The CPU1 holds the supervisory FSM;
  • This supervisory FSM commands the others;
• The cores are running asynchronously;

As far as I know, I have two options:

1. Share variables mapping the same "structure" in the GSRAM to the CPU1 and to the CPU2;
   1. For that I'm using two GSRAMs blocks, one with CPU1 as master and another with CPU2 as master;
2. Use the IPC peripheral and driver to prevent that Reads and Writes occurs at the same time;
   1. For that I think that I would need to use some interrupts, Hwi and Swi;

My doubts:

1. Can sharing variables under the GSRAM lead to memory errors? (I.e., maybe while the CPU1 is writing the CPU2 try to read the same address)
2. If I can't use the GSRAM for that purpose, is there another way to share variables without interrupts? Maybe just use a IPC flag at some point?

Thank in advance, regards,

Lucas