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CCS/F28M36P63C2: Question about TI Concerto F28M36P63C2 and SRAM IS64WV102416DBLL

Mariusz Zyciak24
Prodigy 40 points

Part Number: F28M36P63C2

Tool/software: Code Composer Studio

Hello,

I create a new design (the new PCB) with TI Concerto F28M36P63C2 MCU and SRAM Memory (SRAM Size : 1024 x 16bits (2 MBytes) SRAM configuration : 16 bit data lines and 18 address lines with additional access 8/16 bit mode - for me the access time to the SRAM memory is very important parameter).

My actual configuration is :

SRAM Memory Data lines [ D0...D15 ] <= connect to => MCU TI Concerto F28M36P63C2 Data lines [ EPI0S0 ... EPI0S15 ]

[D0] <=> [EPI0S0]

[D1] <=> [EPI0S1]

....

[D14] <=> [EPI0S14]

[D15] <=> [EPI0S15]

SRAM Memory Address lines [ A0 ... A18 ] <= connect to => MCU TI Concerto F28M36P63C2 lines [ EPI0S16 ... EPI0S24, EPI0S27] and [ EPI0S35 ... EPI0S43 ]

[A0] <=> [EPI0S16]

[A1] <=> [EPI0S17]

....

[A8] <=> [EPI0S24]

[A9] <=> [EPI0S42]

[A10] <=> [EPI0S43]

and

[A11] <=> [EPI0S36]

[A12] <=> [EPI0S37]

[A13] <=> [EPI0S38]

...

[A16] <=> [EPI0S41]

[A17] <=> [EPI0S35]

[A18] <=> [EPI0S27]

SRAM Memory signal [ OE# / WR# / CS# / BSEL0 / BSEL1] <= connect to => MCU TI Concerto F28M36P63C2 lines [ EPI0S28 / EPI0S29 / EPI0S30 / EPI0S25 / EPI0S26]

The EPI0 is configure for {CSCFGEXT + CSCFG} in mode 0x7 (Tri CS Configuration).  Can You tell me which mode {CSCFGEXT + CSCFG} is the best for SRAM memory for this configuration (SRAM configuration : 16 bit data lines and 18 address lines with additional access 8/16 bit mode without multiplex mode).

My question is: Can You check and tell me if above configuration SRAM Memory for MCU TI Concerto F28M36P63C2 it is correct (Yes or No)? 

Thank for Your help.

___

Mariusz Życiak

  • 0
    TI__Guru 62975 points

    Mariusz,

    Have you already designed and built the board with the above signal assignments or are you in the process of trying to determine the mapping?

    If you are still designing, I would recommend working off of Tables 18-5 and 18-7 from the TRM.

    Based on your SRAM description, you would want from Table 18-5:

    • HB16 for 16b SRAM
    • Mode=0x1 for non-muxed address/data
    • {CSCFGEXT + CSCFG}=ANY because you only have one external memory device
    • BSEL=1 for byte-addressability
    • At least 2MB of addressable memory

    Once you eliminate the configurations that will not work, you can reference Table 18-7 for the signal mapping.  If you want to leave room for future upgrades, you can opt for a larger addressable memory range and/or multiple external device support.

    -Tommy

  • 0 in reply to tlee
    Prodigy 40 points

    Thank You for Your help. Yes, I am in the process of trying to determine the mapping of EPI signals (I have a proposal but, I am not 100% sure because this is my first project with TI Concerto F28M36P63C2) - Please look bellow.

    This is my actual configuration (EPI Signals ale selected as a color) :

    What do You think about this configuration? Is it a correct mapping of EPI signals in the TI Concerto F28M36P63C2 (Yes or No)?

    ___

    Mariusz Zyciak

  • 0 in reply to Mariusz Zyciak24
    TI__Guru 62975 points
    Mariusz,

    Can you confirm your memory size? I thought that you had 2MB of memory. The option that you highlighted will only be able to access the first 512kB of memory.

    -Tommy
  • 0 in reply to tlee
    TI__Guru 62975 points
    Mariusz,

    Were you able to confirm the addressable range that you need?

    -Tommy
  • 0 in reply to tlee
    TI__Guru 62975 points
    Mariusz,

    I haven’t heard from you in a a couple of weeks, so I’m assuming you were able to resolve your issue. If this isn’t the case, please reject this resolution and reply to this thread. If this thread locks, please make a new thread describing the current status of your issue.

    -Tommy