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TMS320F28377S: Do Peripheral Registers have ECC or Parity protection?

Eric Ribble93
Prodigy 120 points

Part Number: TMS320F28377S

We are developing an avionics safety-critical product and making used of the ECC/Parity RAM and FLASH of the device.  But it is unclear whether there is any ECC/Parity protection for the CPU Registers and Peripheral Registers to protect/detect Single Event Upsets in them.

sprs881d section 6.3.4 “Peripheral Registers Memory Map” Table 6-5 does not provide any ECC/Parity information.  Do these registers have ECC/Parity protection?

sprs881d section 6.3.5 “Memory Types” Table 6-6 does not provide any ECC/Parity information for the Peripheral Registers.

  • 0
    TI__Guru** 117001 points

    Hi Eric,

    sprs881d section 6.3.4 “Peripheral Registers Memory Map” Table 6-5 does not provide any ECC/Parity information.  Do these registers have ECC/Parity protection?

    No, registers do not have ECC/Parity protection.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 120 points
    Thanks Vivek. We originally selected the TMS320F28377 processor because of its built-in ECC and Parity protection of RAM and FLASH to circumvent Single Event Upsets (SEU) when operating at high altitude. But, if the Peripheral Registers do no have ECC/Parity protection, then we are still very vulnerable to SEU; i.e. a SEU can alter a configuration bit in a Peripheral Register. Perhaps the Peripheral Registers are less susceptible to SEU because of their silicon design (compared to RAM or FLASH)? If anyone has additional information on CPU Registers and Peripheral Registers vulnerability to SEU it would be appreciated. Thanks.
  • 0 in reply to Eric Ribble93
    TI__Guru** 117001 points
    Eric,

    Yes, you rightly mentioned that peripheral registers are less susceptible to SEU but I'll let our safety expert to comment on that and provide more detail if needed.

    Regards,

    Vivek Singh
  • 0 in reply to Vivek Singh
    TI__Intellectual 1110 points

    Hi Eric,

    It is correct that SRAMs are more susceptible to SER due to high energy particles, mainly due to it's physical dimensions.

    Having said this, on F28x37x MCU's, the protection of bit flips on peripherals and processing units (CPU) can be achieved by many safety mechanisms as listed in document "Safety Manual for TMS320F2837xD/S and TMS320F2807x", available under NDA.

    Depending on if the peripheral is control, communication and processing units(CLA and C28x CPU), one or many safety mechanisms listed below from safety manual will be applicable to cover SER failures on register bits.

    • Periodic Software Read Back of Static Configuration Registers
    • Information Redundancy Techniques Including End-to-End Safeing - Communication peripherals
    • Hardware Redundancy - Redundant instance of peripherals
    • Application level or transmission redundancy - Control peripherals
    • Reciprocal Comparison by Software - mainly of processing units C28x and CLA
    • etc. etc.

    Regards,

    --Ashish