TMS320F28375S: SDRAM on EMIF2

Hideaki Nambu

Part Number: TMS320F28375S
Other Parts Discussed in Thread: C2000WARE

Hello,
My customer built an original board. They put an SDRAM on the EMIF2.
They are at an initial stage of its function check.

When they write 0xA5A5 to the EMIF2_CS0n start address, 0x9000:0000, then readback.
The result was 0xA5A5, it was ok, but the problem is, the next address read 0xA5A5 again.

Do you hit any idea why the addr 0x9000:0001 read 0xA5A5?

My customer provided the dump list.
We are trying to gather more data, but it will take several days.
Your advice or checkpoint would be highly appreciated.

over 7 years ago

0 Vivek Singh over 7 years ago

TI__Guru** 115881 points

Hideaki-san,

Can you check the value of NM field in SDRAM_CR register. EMIF2 is 16bit interface hence this should be set to '1'.

Regards,

Vivek Singh

0 tlee over 7 years ago in reply to Vivek Singh

TI__Guru 62975 points

Hideaki-san,

If the SDRAM is still misbehaving after following Vivek's recommendation, the EMIF Application Report also describes an EMIF Configuration Tool in C2000Ware and some common memory fail modes.

-Tommy

0 Hideaki Nambu over 7 years ago in reply to tlee

Mastermind 9165 points

Vivek and tlee,

Thank you for your inputs.

- My customer provided a register dump. I would share.

- From the dump, the NM bitfield was good.

- EMIF configuration tool: I'm working on it.

0 tlee over 7 years ago in reply to Hideaki Nambu

TI__Guru 62975 points

Hideaki-san,

What is the EMIF2 clock frequency? Is it divided down to 100MHz?

-Tommy

0 Hideaki Nambu over 7 years ago in reply to tlee

Mastermind 9165 points

Tommy,
Yes, the EMIF2 clock freq = 100 MHz.

0 Hideaki Nambu over 7 years ago in reply to Hideaki Nambu

Mastermind 9165 points

I would share some data:

- Waveform from the customer setting on Apr-6: I would share some oscilloscope plots. I'm working on them.

- Tommy's New SDRAM setting: No change on memory dump. Nothing better, nothing worse.

/cfs-file/__key/communityserver-discussions-components-files/171/180410.zip

0 tlee over 7 years ago in reply to Hideaki Nambu

TI__Guru 62975 points

Hideaki-san,

Repeated values are common for addressing errors. I recommend writing unique values to each address so that it is easier to identify the faulty signals.

For example:

*0x90000000 = (Uint16)0x0000;
*0x90000001 = (Uint16)0x0001;
*0x90000002 = (Uint16)0x0002;
*0x90000003 = (Uint16)0x0003;
*0x90000004 = (Uint16)0x0004;

....

-Tommy

0 Hideaki Nambu over 7 years ago in reply to tlee

Mastermind 9165 points

My customer tried tommy's test code:

*0x90000000 = (Uint16)0x0000;
*0x90000001 = (Uint16)0x0001;
*0x90000002 = (Uint16)0x0002;
*0x90000003 = (Uint16)0x0003;
*0x90000004 = (Uint16)0x0004;
.
.
*0x90000002 = (Uint32)0x0001;
*0x90000004 = (Uint32)0x0002;
*0x90000006 = (Uint32)0x0003;
*0x90000008 = (Uint32)0x0004;

The code told me that my problem description was not correct.
I'm sorry. Let me revise. (I tried to deescribe but it would be bettter to extract the ZIP file):

/cfs-file/__key/communityserver-discussions-components-files/171/180412-TestCode-Results.zip

[Write and Read in 16bit]
        - The latest written value is mirrored at all the even addresses. Many red values in the memory window.
        - Writing at an even address: The value reads from +1 larger address.
        - Writing at an odd address: The value reads from +1 larger address. The +1 address is even, therefore all the even address mirrors. And they are overwritten in the next step.

[Write and Read in 32bit]
- The written value shifts +16bit, but no more faulty changed locations.

From the result I tried to find a root cause but no good idea. Once I wondered the least address line is opened or fixed to one, but it was not sufficient to explain everything.

Can I ask your idea?

0 tlee over 7 years ago in reply to Hideaki Nambu

TI__Guru 62975 points

Hideaki-san,

32b reads will generate fewer SDRAM instructions (and addresses) than 16b reads. Perhaps one of the signals is transitioning slowly rather than being stuck. Has your customer tried to reduce the EMIF frequency? This would be a good way to check for timing sensitivities.

If a very slow EMIF clock still has problems, I would recommend taking a second look at the signal mapping and pinmux configurations.

-Tommy

0 Hideaki Nambu over 7 years ago in reply to tlee

Mastermind 9165 points

Tommy,
All the errors were removed by a slower clock , or a larger SYSCLKDIVSEL.PLLSYSCLKDIV value.
It would be a timing issue, so I'm reading the SPRAC96 again. The page 9 may be good.

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TMS320F28375S: SDRAM on EMIF2