TMS320F28069: sci tx rx without fifo

hi Ken ,

Please look at the examples in the c2000ware

We do have an example for transmit using interrupts but for internal loopback but using fifos .

Check example device_support\f2806x\examples\c28\scia_loopback_interrupts.

This will need to be modified to not use internal loopback and remove the rx related configurations.

Why do you need an example without fifos?

if its about not filling too much data before you tx then set the tx fifo levels accordingly .

Regards.

hi Ken,

How much data are you sending ? Does it generate when you send more data ?

What data are you sending ?

When you say interrupt is it it doesn't enter the ISR ? Do the interrupt status flags get set ?

The example expects the data to be sent in set of 2 bytes.

Regards.

I don't have all the detail info for now. I think that I didn't see the interrupt on ISR.

I have interrupt when I use without fifo. I am not sure how much data on each interrupt however.

I can check those. If you can provide a setup with FIFO or without FIFO to create a rx int and tx int, It will be helpful.

hi Ken ,

The data you send after which you get an interrupt or you fill in the isr or your configuration for SciaRegs.SCIFFTX.all should tell you how much data is sent after which you would get an interrupt.

No examples as such but can give you some pointers to look at.

To send data into the scitxbuf only with no rx, Use the below example for using interrupts with fifos 

Check example device_support\f2806x\examples\c28\scia_loopback_interrupts.

except :

- without the statement to enable loopback (SciaRegs.SCICCR.bit.LOOPBKENA =1;   // Enable loop back)

- Change SciaRegs.SCICTL1.all =0x0003; to SciaRegs.SCICTL1.all =0x0002; // for only TX 

- Change SciaRegs.SCICTL2.bit.RXBKINTENA =1; to SciaRegs.SCICTL2.bit.RXBKINTENA =0; // No rx.

- Remove configurations related to SCIFFRX in scia_fifo_init().

Use the same example for using interrupts without fifos 

except : 

- remove all of the  content mentioned above for the with fifo case

-  Update SciaRegs.SCIFFTX.all=0xC022; to  SciaRegs.SCIFFTX.all=0x8020; // interrupt when TX level is empty itself ( as if no FIFo).

Let me know how this impacts.

Regards.