Part Number: TMS320F28069
Hello,
In my inverter project , I am comparing two signal (model sine and grid ) out of the DSP . So I need to make a pure sine wave sync with grid so i use SPLL function.
But when i create the sine with PWM DAC (LC filter with PWM) model sine has phase shift with grid. When I compare grid and spll in LC filter output ,they are sync. But I need input grid and output of PWM DAC model sine need to be sync.
https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/191408
I read this post. And I understand that this phase shift is default. So I add a default phase error to the SPLL_1ph_F_FUNC phase detect block. But it did not satisfy me.
Does this error guarantee synchronization? Or how can I handle this default error.
//*********** Function Definition ********//
void SPLL_1ph_F_FUNC(SPLL_1ph_F *spll_obj)
{
//-------------------//
// Phase Detect //
//-------------------//
spll_obj->Upd[0]=(spll_obj->AC_input*spll_obj->cos[1])-0.07;