• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 642 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280049: CAN CLK question

Joe Zhu
Intellectual 2540 points

Part Number: TMS320F280049
Other Parts Discussed in Thread: C2000WARE

Hi Champion,

I have two question about CAN CLK:

1. Baud rate = CAN clock / {[(BRP + 1)+(BRPE *64)]*(Tseg1 + Tseg2 + 1)}, so in CAN CTR register, Tseg1 = Tseg2  or Tseg1 + 1 = Tseg2 and TSJW = min(Tseg1 ,Tseg2, 4), right?

2. After test, no matter we config 

ClkCfgRegs.CLKSRCCTL2.bit.CANBBCLKSEL = 0 or 1 CAN clock also same, for example 10MHz, but this bit is decide CAN clock source sysclk(100MHz) or crystal(10MHz), this two clk sorue is 10x gap, why CAN final clock is same?

Thanks!

BR

Joe

  • 0
    TI__Mastermind 30255 points
    Joe

    For timing, refer to this: http://www.ti.com/lit/sprac35

    I believe that should be the only thing that needs to be changed. Have you tried this with a C2000Ware example and seen if the clock changes?

    Best regards
    Chris
  • 0 in reply to Christopher Chiarella
    TI__Intellectual 2540 points
    Hi Chris,

    Same result with C200WARE, you can try to verify. So we confuse about it. For question one, I want to confirm my suppose is right? We have read the userguid yo attach.

    Thanks!
    BR
    Joe
  • 0 in reply to Joe Zhu
    TI__Mastermind 30255 points
    Joe

    The equation can change based on which CAN bit rate values are being set so can't confidently confirm. Have you used the excel calculation sheet that is part of that app note? If not, it provides a detailed calculation and the value to set in the BTR register. Additionally, you can refer to the CAN driverlib to see how we are calculating these based off the desired bit rate.

    I tested the CAN example from C2000Ware, configured it to use the SYSCLK (100MHz) and then XTAL (20MHz on controlCARD), I saw the bus bit rate change from 500khz to ~100khz. I observed it by measuring the smallest single pulse as part of a CAN message transmitted. The SYSCLK one was 1.92us wide and the XTAL one was 9.61us wide.

    Best regards
    Chris