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TIDM-1000: DCL-Capacitor Calculation?

Lukas Jani
Prodigy 190 points

Part Number: TIDM-1000

Hello,

i'd have a question about the DCL-Capacitor Formula which is given in the TIDM-1000 White Paper.

You calculate the capacitor for a given sinusoidal current. With a constant powerflow in a three-phase system, i suppose  you dont need any capacitor in de DC-Link. (ideally). The capacitance is only needed to cover gaps in the powerflow because of switch deadtimes, zerovector, laodsteps etc. Am i right here? If yes, is there any calculation or formula given for this case? i dont see any dependence on the switching frequency here, which would be crucial for the voltage controller. 

Thank you for your help,

best regards,

Lukas

  • 0
    TI__Mastermind 43730 points
    Lukas,

    Yes you are correct, the equation given in the app note will result in a over design. Typically the cap is sized based on load requirements. As we only did the rectifier stage and the load can be anything we had to choose some design paramater to size it.

    In an updated version of that report we will get this corrected, this is under works already. It is on track to be published by end of June 2018. (We only update once a quater for the app reports).

    I found this to be a very helpfull paper

    www.ecicaps.com/.../IEMDC_2009_11310_Final_Rev_4.pdf
  • 0 in reply to Manish Bhardwaj
    Prodigy 10 points
    Good Morning,
    thank you for your help. I've look at the paper you linked. According to his calculation, the actual bus capacitance needed is very minimal for similar applications (to the TIDM1000).
    Another interesting read is the Ph.D. Thesis of Mariusz Cichowlas "PWM Rectifier with Active Filter".
    icg.isep.pw.edu.pl/.../mariusz_cichowlas.pdf
    He estimates the capacitor size in the DCL for a SVPWM-Rectifier. See Page 75.
    Following my Simulation of a three-phased PWM-Rectifier, the capacitance-value given in the paper you linked is sufficient, but no controller modell was implemented here. (Sim with LTSpice).
    A critical point according to an experienced engineer at my company is the stability of the voltage control loop, which might have time constants of nearly seconds, rather than 1/fs. For load-jumps, this might be worth an investigation.

    Anyway, im looking forward to the newly written paper you hinted!
    best regards,
    Lukas
  • 0 in reply to Lukas Jani3
    TI__Mastermind 43730 points
    Lukas,

    thanks for the helpfull pointers.

    regards
    Manish Bhardwaj