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Tool/software: Code Composer Studio
Hello,
I use Launchxl f28069m kit. I have a "number" struct for 99 numbers and each number struct obtains 15 parameters (uint16, float etc). I need all these 99x15 parameter values to be kept in a retentive (or a non-volatile) memory. Is it possible with this kit or should I use an external EEPROM? If the kit has this feature, I think I need a full memory map, big endian / little endian addressing protocol documentations.
Hmm I thought that would solve my problem. But then checked the topic below :
e2e.ti.com/.../419551
"As a general statement, the flash is intended to store code, and was not designed for frequent storing of data. In order to change a single word in flash, you need to erase the entire flash sector."
Mr. Alter seems right. I will change the struct parameter values frequently. I should not erase the entire flash sector.
Where do you store your user defined parameters in similar kind of designs?
I don't have any experience about memory mapping but this code carries my struct addresses perfectly.
#pragma SET_DATA_SECTION(".econst") //.econst or any others
struct PROGRAM
{
Uint16 aParameter;
Uint16 bParameter;
Uint16 cParameter;
float32 dParameter;
Uint16 eParameter;
Uint16 fParameter;
float32 gParameter;
Uint16 hParameter;
Uint16 iParameter;
Uint16 jParameter;
Uint16 kParameter;
Uint16 lParameter;
float32 mParameter;
Uint16 nParameter;
Uint16 oParameter;
};
struct PROGRAM number [99];
#pragma SET_DATA_SECTION()
But I don't know where to carry as non-volatile user defined parameters. I have 2 cmd files.
F2806x_FLASH_SymmetricPWM.CMD is below :
/*==================================================================================*/
/* User specific Linker command file for running from FLASH */
/*==================================================================================*/
/* FILE: F2806x_FLASH_SymmetricPWM.CMD
/* */
/* Description: Linker command file for User custom sections targetted to run */
/* from FLASH. */
/* */
/* Target: TMS320F2806x */
/* */
/* Version: 1.0 */
/* */
/*----------------------------------------------------------------------------------*/
/* Copyright Texas Instruments © 2010 */
/*----------------------------------------------------------------------------------*/
/* Revision History: */
/*----------------------------------------------------------------------------------*/
/* Date | Description */
/*----------------------------------------------------------------------------------*/
/* 01/11/11 | Release 1.0 */
/*----------------------------------------------------------------------------------*/
/* Define the memory block start/length for the F2806x
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F2806x are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
The L0 memory block is mirrored - that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Continuous SARAM memory blocks or flash sectors can be
combined if required to create a larger memory block.
*/
MEMORY
{
PAGE 0:
/* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
progRAM : origin = 0x008000, length = 0x000C00
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHH : origin = 0x3D8000, length = 0x004000 /* on-chip FLASH */
FLASHG : origin = 0x3DC000, length = 0x004000 /* on-chip FLASH */
FLASHF : origin = 0x3E0000, length = 0x004000 /* on-chip FLASH */
FLASHE : origin = 0x3E4000, length = 0x004000 /* on-chip FLASH */
FLASHD : origin = 0x3E8000, length = 0x004000 /* on-chip FLASH */
FLASHC : origin = 0x3EC000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
FPUTABLES : origin = 0x3FD860, length = 0x0006A0 /* FPU Tables in Boot ROM */
IQTABLES : origin = 0x3FDF00, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEA50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEADC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
BOOTROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 :
/* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
dataRAM : origin = 0x008C00, length = 0x001400
RAML4 : origin = 0x00A000, length = 0x002000 /* on-chip RAM block L4 */
RAML5 : origin = 0x00C000, length = 0x002000 /* on-chip RAM block L5 */
RAML6 : origin = 0x00E000, length = 0x002000 /* on-chip RAM block L6 */
RAML7 : origin = 0x010000, length = 0x002000 /* on-chip RAM block L7 */
RAML8 : origin = 0x012000, length = 0x002000 /* on-chip RAM block L8 */
FLASHB : origin = 0x3F4000, length = 0x002000
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA, PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA, PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHA,
RUN = progRAM,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0, PAGE = 1
.ebss : > dataRAM, PAGE = 1
.esysmem : > dataRAM, PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHA PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES PAGE = 0, TYPE = NOLOAD /* Math Tables In ROM */
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
}
SECTIONS
{
Net_terminals: > dataRAM,PAGE = 1
}
F2806x_Headers_nonBIOS.cmd is below :
/*
// TI File $Revision: /main/2 $
// Checkin $Date: January 4, 2011 10:00:20 $
//###########################################################################
//
// FILE: F2806x_Headers_nonBIOS.cmd
//
// TITLE: F2806x Peripheral registers linker command file
//
// DESCRIPTION:
//
// This file is for use in Non-BIOS applications.
//
// Linker command file to place the peripheral structures
// used within the F2806x headerfiles into the correct memory
// mapped locations.
//
// This version of the file includes the PieVectorTable structure.
// For BIOS applications, please use the F2806x_Headers_BIOS.cmd file
// which does not include the PieVectorTable structure.
//
//###########################################################################
// $TI Release: 2806x C/C++ Header Files and Peripheral Examples V1.00 $
// $Release Date: January 11, 2011 $
//###########################################################################
*/
MEMORY
{
PAGE 0: /* Program Memory */
PAGE 1: /* Data Memory */
DEV_EMU : origin = 0x000880, length = 0x000105 /* device emulation registers */
SYS_PWR_CTL : origin = 0x000985, length = 0x000003 /* System power control registers */
FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */
CSM : origin = 0x000AE0, length = 0x000020 /* code security module registers */
ADC_RESULT : origin = 0x000B00, length = 0x000020 /* ADC Results register mirror */
CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */
CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */
PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */
DMA : origin = 0x001000, length = 0x000200 /* DMA Registers */
CLA1 : origin = 0x001400, length = 0x000080 /* CLA Registers */
McBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A Register */
ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */
ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */
ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */
ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */
ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */
COMP1 : origin = 0x006400, length = 0x000020 /* Comparator + DAC 1 registers */
COMP2 : origin = 0x006420, length = 0x000020 /* Comparator + DAC 2 registers */
COMP3 : origin = 0x006440, length = 0x000020 /* Comparator + DAC 3 registers */
EPWM1 : origin = 0x006800, length = 0x000040 /* Enhanced PWM 1 registers */
EPWM2 : origin = 0x006840, length = 0x000040 /* Enhanced PWM 2 registers */
EPWM3 : origin = 0x006880, length = 0x000040 /* Enhanced PWM 3 registers */
EPWM4 : origin = 0x0068C0, length = 0x000040 /* Enhanced PWM 4 registers */
EPWM5 : origin = 0x006900, length = 0x000040 /* Enhanced PWM 5 registers */
EPWM6 : origin = 0x006940, length = 0x000040 /* Enhanced PWM 6 registers */
EPWM7 : origin = 0x006980, length = 0x000040 /* Enhanced PWM 7 registers */
EPWM8 : origin = 0x0069C0, length = 0x000040 /* Enhanced PWM 8 registers */
ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */
ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */
ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */
EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */
EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */
GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */
GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */
GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */
SYSTEM : origin = 0x007010, length = 0x000030 /* System control registers */
SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */
SPIB : origin = 0x007740, length = 0x000010 /* SPI-B registers */
SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */
SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */
NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */
XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */
ADC : origin = 0x007100, length = 0x000080 /* ADC registers */
I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */
PARTID : origin = 0x3D7E80, length = 0x000001 /* Part ID register location */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */
}
SECTIONS
{
/*** PIE Vect Table and Boot ROM Variables Structures ***/
UNION run = PIE_VECT, PAGE = 1
{
PieVectTableFile
GROUP
{
EmuKeyVar
EmuBModeVar
FlashCallbackVar
FlashScalingVar
}
}
/*** Peripheral Frame 0 Register Structures ***/
DevEmuRegsFile : > DEV_EMU, PAGE = 1
SysPwrCtrlRegsFile: > SYS_PWR_CTL, PAGE = 1
FlashRegsFile : > FLASH_REGS, PAGE = 1
CsmRegsFile : > CSM, PAGE = 1
AdcResultFile : > ADC_RESULT, PAGE = 1
CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1
PieCtrlRegsFile : > PIE_CTRL, PAGE = 1
Cla1RegsFile : > CLA1, PAGE = 1
DmaRegsFile : > DMA, PAGE = 1
/*** Peripheral Frame 1 Register Structures ***/
ECanaRegsFile : > ECANA, PAGE = 1
ECanaLAMRegsFile : > ECANA_LAM, PAGE = 1
ECanaMboxesFile : > ECANA_MBOX, PAGE = 1
ECanaMOTSRegsFile : > ECANA_MOTS, PAGE = 1
ECanaMOTORegsFile : > ECANA_MOTO, PAGE = 1
ECap1RegsFile : > ECAP1, PAGE = 1
ECap2RegsFile : > ECAP2, PAGE = 1
ECap3RegsFile : > ECAP3, PAGE = 1
EQep1RegsFile : > EQEP1, PAGE = 1
EQep2RegsFile : > EQEP2, PAGE = 1
GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1
GpioDataRegsFile : > GPIODAT, PAGE = 1
GpioIntRegsFile : > GPIOINT, PAGE = 1
/*** Peripheral Frame 2 Register Structures ***/
SysCtrlRegsFile : > SYSTEM, PAGE = 1
SpiaRegsFile : > SPIA, PAGE = 1
SpibRegsFile : > SPIB, PAGE = 1
SciaRegsFile : > SCIA, PAGE = 1
ScibRegsFile : > SCIB, PAGE = 1
NmiIntruptRegsFile: > NMIINTRUPT, PAGE = 1
XIntruptRegsFile : > XINTRUPT, PAGE = 1
AdcRegsFile : > ADC, PAGE = 1
I2caRegsFile : > I2CA, PAGE = 1
/*** Peripheral Frame 3 Register Structures ***/
Comp1RegsFile : > COMP1, PAGE = 1
Comp2RegsFile : > COMP2, PAGE = 1
Comp3RegsFile : > COMP3, PAGE = 1
EPwm1RegsFile : > EPWM1, PAGE = 1
EPwm2RegsFile : > EPWM2, PAGE = 1
EPwm3RegsFile : > EPWM3, PAGE = 1
EPwm4RegsFile : > EPWM4, PAGE = 1
EPwm5RegsFile : > EPWM5, PAGE = 1
EPwm6RegsFile : > EPWM6, PAGE = 1
EPwm7RegsFile : > EPWM7, PAGE = 1
EPwm8RegsFile : > EPWM8, PAGE = 1
McbspaRegsFile : > McBSPA, PAGE = 1
/*** Code Security Module Register Structures ***/
CsmPwlFile : > CSM_PWL, PAGE = 1
/*** Device Part ID Register Structures ***/
PartIdRegsFile : > PARTID, PAGE = 1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
I don't know why I have 2, I don't know if both are necessary but I have merged some examples.
Now as I understand I can carry my struct to areas like .stack, .ebss but I don't want RAM, I need something like .econst which is PAGE = 0 programming area of flash and does not let me change the values of parameters. (All parameters become "0")
I need a suitable area for my non-volatile and changeable parameters. (Will be PAGE = 1 but will be retained, not RAM)
