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CCS/TMS320F28069: Priority of interrupts

Devvrat Arya56
Prodigy 110 points

Part Number: TMS320F28069

Tool/software: Code Composer Studio

If I am using more than one interrupt in my application( like timer and UART) . What will be the default priority of those interrupt

  • 0
    TI__Genius 17315 points
    Devvrat,

    Please see the F2806x Technical Reference Manual (SPRUH18), starting on page 176, tables 1-119 and 1-120:

    www.ti.com/lit/spruh18.pdf

    Also, to learn more about the F2806x interrupt please see the F2806x workshop at:

    processors.wiki.ti.com/.../C2000_Archived_Workshops

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • 0
    TI__Guru 61235 points

    Devvrat,

    Interrupt priority is documented in the device datasheet. For the PIE, interrupt group 1 is highest priority. Within a group, interrupt 1 is highest priority.

    However, understand that priority only applies when more than one interrupt is pending at the same time. Once you are in an ISR, ANY enabled interrupt can interrupt that ISR. By default, global interrupt enable (INTM bit) is disabled when entering an ISR. To nest interrupts, you need to enable any desired interrupts, disable all other interrupts (using IER and PIEIER registers), and then re-enable global interrupts.

    Regards,
    David

  • 0 in reply to David M. Alter
    TI__Genius 17315 points
    Devvrat,

    Sorry, the link to the document should be:

    www.ti.com/lit/spruh18

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • 0 in reply to Ken Schachter
    TI__Genius 17315 points
    Devvrat,

    I haven’t heard from you for a while, so I’m assuming you were able to resolve your issue. If this isn’t the case, please reject this resolution or reply to this thread. If this thread locks, please make a new thread describing the current status of your issue.

    - Ken