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Can one define which RAM blocks has to be used for fetch, read, and write.
Say in the IDE, (CCS) could all be defined as internal, different RAM blocks
Any help appreciated
Gerhard,
The libraries will work on either a dual or a single core part. It's only that the examples were prepared on a dual core F2837xD board.
If you have a CCS project prepared for the single core part you should be able to use the library without difficulty by following the steps in chapter 4. Please post back here if you run into any difficulty.
Regards,
Richard