TMS320F28379S: Trying to build an 8 phase full H bridge driver with Duty cycle, Frequency, Chopping , Phase direction and Current limit controller for a 7 MEGAWATT 8 phase motor drive.

What is the problem?

So method #1 is where I have the period set to 10000 for all 8 ePWM's.
I set the phase register to stagger them by 1/4 of a half cycle. 8 in total.
The problem with that strategy is that #1 can count all the way to 10000,
#2 can only count 7500 and #3.... and so on. Well when they get to 1000 the cycle starts over.
so #1 is good. Meaning I get a full cycle of 50% duty cycle. However #2, #3... all are shortened.
SO I dont get 50% duty cycle on them only #1.

So I tried another method.
I set a counter to compare of the cycle time 1/8 time. That generated an interrupt.
In the ISR I set the time base counter of the next PWM in line to 0. So it is now essentially
starting to count 1/8 of the phase of the preceding PWM. SO now each PWM can count to the full
cycle count of 10000 and then repeat. Well that produced a "sliding" output for #2, #3 and so on...
The scope was triggered on PWM #1 output but all the remaining outputs were shifting in time slowly
because there is a one cycle difference between the #1 counter value and all the others. Each waveform
was sliding relative to its neighbor slowly - by one count per interrupt.

Anyway lets start with that. I tried a couple of other ways by the they also produced other unacceptable
results like s 180 degree shift in phase randomly and stuff like that.

I am hoping that somebody has been round the block on something like this.

One of the main problems results from the fact that the PWM's are set up to trigger one after another
but only in groups of three. No way to get the trigger output from the third one into a fourth etc. That
is just the way the chip is set up. Clearly it was designed for multiple 3 phase motors - I mean why would you
want to anything else? I mean nobody has ever heard of an 8 phase motor - right?

Anyway if you have any ideas I would love to get into it with you.

Thanks, Dave.

Hi Dave,

Your method #1 should have worked fine. I am going to assume a few things here and provide a couple of suggestions that might help. PWM1 can be the master for all 8 PWMs, if that is okay for your application, or at least for PWMs 2,3,4, and 7 (following the synchronization scheme available on this device). Use a TBPRD value of 10000 for PWM1, but use a TBPRD value of 9999 for all the slave PWMs. Follow the same logic if you decide to sync PWMs 5 and 6 with PWM4 (instead of PWM1) and PWM8 with PWM7 and so on (you get the idea..).

Because of the phase synchronization you should still get the correct PWM frequency at each output.

Let me know how this goes or if I am missing something.

Hrishi 

I have done what you suggested.

I am only implementing 4 PWM channels since I only have 4 channels on my scope.
I am seeing the same issue now that I have before where the highest PWM channel "locks up" and quits producing the waveform
when I reach a specific phase number.

When I get to a phase number (my code variable PHN) between 0 to 3333 produces an output but when PHN is >= 3334 the 4th channel stops.

I have the ability to change the phasing because this drive must ultimately be able to drive 4 or 8 phase motors. So the phase
has to be adjustable between 4 or 8 slices per rotation. My code takes a number between 0 to 5000 where 5000 is used
for a 4 phase motor and a number of 2500 is used on 8 phase motors. And of course the phase is variable from 0 to 5000 so
I can slowly increase the phase and make sure all channels operate properly.

I also need to reverse the rotation of the motor so I need to be able to reverse the sequence of all the channels. I have code
for that implemented and one some of my attempts it worked properly nut not in others.

What I have running now is close but for the lockup situation. I think the best thing to do now to save time is have you share
my desktop and camera so I can work directly and you can see for yourself what is going on.

I will attach my code so you have a reference of how I have implemented things. Sorry it is about 1300 lines not including
all the includes from the example project that I started from which was located here;

C:\ti\C2000Ware_1_00_04_00_Software\device_support\f2837xs\examples\cpu1\epwm_deadband\cpu01


Seems the attachment function is not working so I will just append the code starting here;





//========================================================================
// Included Files
//========================================================================
#include "F28x_Project.h"


//========================================================================
// Defines
//========================================================================
#define EPWMx_MAX_DB 0x03FF
#define EPWMx_MIN_DB 0
#define DB_UP 1
#define DB_DOWN 0

#define PWM1 0
#define PWM2 1
#define PWM3 2
#define PWM4 3
#define PWM5 4
#define PWM6 5
#define PWM7 6
#define PWM8 7


//========================================================================
// Globals
//========================================================================
Uint32 EPwm1TimerIntCount;
Uint32 EPwm2TimerIntCount;
Uint32 EPwm3TimerIntCount;
Uint32 EPwm4TimerIntCount;
Uint32 EPwm5TimerIntCount;
Uint32 EPwm6TimerIntCount;
Uint32 EPwm7TimerIntCount;
Uint32 EPwm8TimerIntCount;

bool led_ctrl;
bool Phases;
Uint16 Period;
Uint32 Freq;
Uint32 Cycle_Width = 500;
Uint16 Phase;
Uint16 Dead_Band;
Uint16 Chop_Freq;
Uint16 Chop_Duty;
Uint16 Tach;
Uint16 PHN;
Uint16 FWD_REV;

//========================================================================
// Function Prototypes
//========================================================================

void Init_System();

void Init_EPwm1(void);
void Init_EPwm2(void);
void Init_EPwm3(void);
void Init_EPwm4(void);
void Init_EPwm5(void);
void Init_EPwm6(void);
void Init_EPwm7(void);
void Init_EPwm8(void);

__interrupt void epwm1_isr(void);
__interrupt void epwm2_isr(void);
__interrupt void epwm3_isr(void);
__interrupt void epwm4_isr(void);
__interrupt void epwm5_isr(void);
__interrupt void epwm6_isr(void);
__interrupt void epwm7_isr(void);
__interrupt void epwm8_isr(void);



//========================================================================
// Main
//========================================================================
void main(void)
{

Init_System (); // Init the system

Freq = 10000; // MISC. Initialization stuff
Cycle_Width = 5000;
Phases = 1;




//========================================================================
// Step 6. IDLE loop. Just sit and loop forever (optional):
//========================================================================

while (1)
{
EALLOW;

//--------------- Apply Cycle Width Limits ---------------------
if (Cycle_Width >= Freq) {Cycle_Width = Freq - 1;}
if (Cycle_Width <= 500 ) {Cycle_Width = 500;}

//---------------------- Frequency Control ---------------------
EPwm1Regs.TBPRD = Freq; // Frequency Control
EPwm2Regs.TBPRD = Freq - 1; // Frequency Control
// EPwm3Regs.TBPRD = Freq - 1; // Frequency Control
// EPwm4Regs.TBPRD = Freq - 1; // Frequency Control
// EPwm5Regs.TBPRD = Freq - 1; // Frequency Control
// EPwm6Regs.TBPRD = Freq - 1; // Frequency Control
// EPwm7Regs.TBPRD = Freq - 1; // Frequency Control
// EPwm8Regs.TBPRD = Freq - 1; // Frequency Control

EPwm1Regs.CMPA.bit.CMPA = Cycle_Width;
EPwm1Regs.CMPB.bit.CMPB = Freq - Cycle_Width ; // Make SYNC Pulse

//


Tach = Freq;

EPwm1Regs.PCCTL.bit.CHPDUTY = Chop_Duty; // Duty Cycle
EPwm1Regs.PCCTL.bit.CHPFREQ = Chop_Freq; // Frequency
EPwm1Regs.PCCTL.bit.CHPEN = led_ctrl; // Enable
EPwm1Regs.PCCTL.bit.OSHTWTH = 0xf; // Initial pulse width

EDIS;

/*
//-------------------- Handle Phasing of each PWM CHannel -------------------------
if (!Phases) {PHN = (Freq/2) - 1;} else {PHN = (Freq/4) -1;} // Phase control 2 = 4 phase 4 = 8 phase
if (Phase >= Freq/2) {Phase = (Freq/2) - 1;} // Clamp the Phase
if (Phase) {PHN = Phase -1;} // VAriable Phase control



EPwm1Regs.TBPHS.bit.TBPHS = 0; // Set Phase
EPwm2Regs.TBPHS.bit.TBPHS = PHN; // Set Phase
EPwm3Regs.TBPHS.bit.TBPHS = PHN * 2; // Set Phase
EPwm4Regs.TBPHS.bit.TBPHS = PHN * 3; // Set Phase
*/

//-------------------- Handle Phase Direction -----------------------------
if (!FWD_REV){ // --------------- Forward Direction ------------------
EALLOW;

EPwm1Regs.TBPHS.bit.TBPHS = 0; // Set Phase
EPwm2Regs.TBPHS.bit.TBPHS = PHN; // Set Phase
EPwm3Regs.TBPHS.bit.TBPHS = PHN * 2; // Set Phase
EPwm4Regs.TBPHS.bit.TBPHS = PHN * 3; // Set Phase
}
else {
EPwm1Regs.TBPHS.bit.TBPHS = PHN * 3; // Set Phase
EPwm2Regs.TBPHS.bit.TBPHS = PHN * 2; // Set Phase
EPwm3Regs.TBPHS.bit.TBPHS = PHN; // Set Phase
EPwm4Regs.TBPHS.bit.TBPHS = 0; // Set Phase

}
/*
EPwm1Regs.DBCTL.bit.OUTSWAP = 0; // Polarity Select Control
EPwm2Regs.DBCTL.bit.OUTSWAP = 0; // Polarity Select Control
EPwm3Regs.DBCTL.bit.OUTSWAP = 0; // Polarity Select Control
EPwm4Regs.DBCTL.bit.OUTSWAP = 0; // Polarity Select Control
EPwm5Regs.DBCTL.bit.OUTSWAP = 0; // Polarity Select Control
EPwm6Regs.DBCTL.bit.OUTSWAP = 0; // Polarity Select Control
EPwm7Regs.DBCTL.bit.OUTSWAP = 0; // Polarity Select Control
EPwm8Regs.DBCTL.bit.OUTSWAP = 0; // Polarity Select Control
}
else {
EPwm1Regs.DBCTL.bit.OUTSWAP = 3; // Polarity Select Control
EPwm2Regs.DBCTL.bit.OUTSWAP = 3; // Polarity Select Control
EPwm3Regs.DBCTL.bit.OUTSWAP = 3; // Polarity Select Control
EPwm4Regs.DBCTL.bit.OUTSWAP = 3; // Polarity Select Control
EPwm5Regs.DBCTL.bit.OUTSWAP = 0; // Polarity Select Control
EPwm6Regs.DBCTL.bit.OUTSWAP = 0; // Polarity Select Control
EPwm7Regs.DBCTL.bit.OUTSWAP = 0; // Polarity Select Control
EPwm8Regs.DBCTL.bit.OUTSWAP = 0; // Polarity Select Control
}
*/

EDIS;


//-------------------------- LED Stuff -----------------------------------
GPIO_WritePin(31, 0); // Turn on LED
if (led_ctrl){GPIO_WritePin(34, 1);}
// DELAY_US(1000*100); // Delay for a bit.
GPIO_WritePin(31, 1); // Turn off LED
if (!led_ctrl){GPIO_WritePin(34, 0);}
// DELAY_US(1000*100); // Delay for a bit.

}
}


//========================================================================
// epwm1_isr - EPWM1 ISR
//========================================================================
__interrupt void epwm1_isr(void)
{
// EALLOW;
// CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
// EDIS;

// EPwm2Regs.TBCTR = PHN; // Clear counter
// EPwm3Regs.TBCTR = PHN * 2; // Clear counter
// EPwm4Regs.TBCTR = PHN * 3; // Clear counter
// EPwm5Regs.TBCTR = 0; // Clear counter
// EPwm6Regs.TBCTR = PHN; // Clear counter
// EPwm7Regs.TBCTR = PHN * 2; // Clear counter
// EPwm8Regs.TBCTR = PHN * 3; // Clear counter

// EALLOW;
// CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
// EDIS;


// EPwm5Regs.TBCTR = PHN; // Clear counter


EPwm1TimerIntCount++;
EPwm1Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm1Regs.ETCLR.bit.INT = 1; // Clear INT flag for this timer
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; // Acknowledge this interrupt
}

//========================================================================
// epwm2_isr - EPWM2 ISR
//========================================================================
__interrupt void epwm2_isr(void)
{
// EPwm3Regs.TBCTR = PHN; // Clear counter
// EPwm6Regs.TBCTR = PHN; // Clear counter
EPwm2TimerIntCount++;
EPwm2Regs.TBPHS.bit.TBPHS = PHN; // Set Phase
EPwm2Regs.ETCLR.bit.INT = 1; // Clear INT flag for this timer
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; // Acknowledge this interrupt
}

//========================================================================
// epwm3_isr - EPWM3 ISR
//========================================================================
__interrupt void epwm3_isr(void)
{
// EPwm4Regs.TBCTR = PHN; // Clear counter
// EPwm7Regs.TBCTR = PHN; // Clear counter
EPwm3TimerIntCount++;
EPwm3Regs.TBPHS.bit.TBPHS = PHN * 2; // Set Phase
EPwm3Regs.ETCLR.bit.INT = 1; // Clear INT flag for this timer
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; // Acknowledge this interrupt
}

//========================================================================
// epwm4_isr - EPWM4 ISR
//========================================================================
__interrupt void epwm4_isr(void)
{
// EPwm5Regs.TBCTR = PHN; // Clear counter
// EPwm8Regs.TBCTR = PHN; // Clear counter
EPwm4TimerIntCount++;
EPwm4Regs.TBPHS.bit.TBPHS = PHN * 3; // Set Phase
EPwm4Regs.ETCLR.bit.INT = 1; // Clear INT flag for this timer
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; // Acknowledge this interrupt
}

//========================================================================
// epwm1_isr - EPWM5 ISR
//========================================================================
__interrupt void epwm5_isr(void)
{
// EPwm6Regs.TBCTR = PHN; // Clear counter
EPwm5TimerIntCount++;
EPwm5Regs.ETCLR.bit.INT = 1; // Clear INT flag for this timer
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; // Acknowledge this interrupt
}

//========================================================================
// epwm6_isr - EPWM6 ISR
//========================================================================
__interrupt void epwm6_isr(void)
{
// EPwm7Regs.TBCTR = PHN; // Clear counter
EPwm6TimerIntCount++;
EPwm6Regs.ETCLR.bit.INT = 1; // Clear INT flag for this timer
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; // Acknowledge this interrupt
}

//========================================================================
// epwm7_isr - EPWM7 ISR
//========================================================================
__interrupt void epwm7_isr(void)
{
// EPwm8Regs.TBCTR = PHN; // Clear counter
EPwm7TimerIntCount++;
EPwm7Regs.ETCLR.bit.INT = 1; // Clear INT flag for this timer
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; // Acknowledge this interrupt
}

//========================================================================
// epwm8_isr - EPWM8 ISR
//========================================================================
__interrupt void epwm8_isr(void)
{
EPwm8TimerIntCount++;
EPwm8Regs.ETCLR.bit.INT = 1; // Clear INT flag for this timer
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; // Acknowledge this interrupt
}






//========================================================================
// InitEPwm1Example - Initialize EPWM1 configuration
//========================================================================
void Init_EPwm1()
{
/*
//-------------- Simultanious Register Write Linkages ---------------
EPwm1Regs.EPWMXLINK.bit.TBPRDLINK = 0; // TBPRD Link
EPwm1Regs.EPWMXLINK.bit.CMPALINK = 0; // CMP A Link
EPwm1Regs.EPWMXLINK.bit.CMPBLINK = 0; // CMP B Link
EPwm1Regs.EPWMXLINK.bit.CMPCLINK = 0; // CMP C Link
EPwm1Regs.EPWMXLINK.bit.CMPDLINK = 0; // CMP D Link
EPwm1Regs.EPWMXLINK.bit.GLDCTL2LINK = 0; //
*/
/*
//--------------- Global Load Configuration Registers ---------------
EPwm1Regs.GLDCFG.bit.TBPRD_TBPRDHR = 1; // TBPRD
EPwm1Regs.GLDCFG.bit.CMPA_CMPAHR = 1; // Compare A
EPwm1Regs.GLDCFG.bit.CMPB_CMPBHR = 1; // Compare B
EPwm1Regs.GLDCFG.bit.CMPC = 0; // Compare C
EPwm1Regs.GLDCFG.bit.CMPD = 0; // Compare D
EPwm1Regs.GLDCFG.bit.DBCTL = 1; // Dead Band Control
EPwm1Regs.GLDCFG.bit.DBRED_DBREDHR = 1; // DB Rising
EPwm1Regs.GLDCFG.bit.DBFED_DBFEDHR = 1; // DB Falling
EPwm1Regs.GLDCFG.bit.AQCTLA_AQCTLA2 = 0; // AQCTLA/A2
EPwm1Regs.GLDCFG.bit.AQCTLB_AQCTLB2 = 0; // AQCTLB/B2
EPwm1Regs.GLDCFG.bit.AQCSFRC = 0; // AQCSFRC
*/

//------------------- Time Base Register ----------------------------
EPwm1Regs.TBPRD = 10000; // Set time Base period
EPwm1Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm1Regs.TBCTR = 0; // Clear counter

//------------------- Time Base Clock -------------------------------
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Counter Mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Phase Load Enable
EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP; // Phase Direction Bit
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Active Period Load
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Time Base Clock Pre-scaler
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // SYNC out selection
EPwm1Regs.TBCTL.bit.SWFSYNC = 0; // Software Force Sync Pulse
EPwm1Regs.TBCTL.bit.FREE_SOFT = 0; // Emulation Mode Bits

//------------------- Shadow Register Actions -----------------------
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; //
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; //
/*
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE; //
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE; //
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; //
*/

//---------------------- Counter Compare ----------------------------
EPwm1Regs.CMPA.bit.CMPA = 2500; // CTR = CMPA
EPwm1Regs.CMPB.bit.CMPB = 7500; // CTR = CMPB
EPwm1Regs.CMPC = 2222; // CTR = CMPC
EPwm1Regs.CMPD = 2222; // CTR = CMPD

//---------------------- Action Qualifiers --------------------------
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A to One
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; //
EPwm1Regs.AQCTLB.bit.PRD = AQ_SET; // Set PWM1B to Zero
EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR; //

//------------- Active Low PWMs - Setup Deadband -------------------
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HI; // Polarity Select Control
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE; // Output Mode Control
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; // Input Select Mode Control
EPwm1Regs.DBCTL.bit.LOADREDMODE = 0; // Active DBRED Load Mode
EPwm1Regs.DBCTL.bit.LOADFEDMODE = 0; // Active DBFED Load Mode
EPwm1Regs.DBCTL.bit.SHDWDBREDMODE = 0; // DBRED Block Operating Mode
EPwm1Regs.DBCTL.bit.SHDWDBFEDMODE = 0; // DBFED Block Operating Mode
EPwm1Regs.DBCTL.bit.OUTSWAP = 0; // Output Swap Control
EPwm1Regs.DBCTL.bit.DEDB_MODE = 1; // Dual-Edge B Mode Control
EPwm1Regs.DBCTL.bit.HALFCYCLE = 0; // Half Cycle Clocking Enable

//------------------ Dead Band Timing Values ------------------------
EPwm1Regs.DBRED.bit.DBRED = EPWMx_MIN_DB; // Set Rising edge delay
EPwm1Regs.DBFED.bit.DBFED = EPWMx_MIN_DB; // Set falling edge delay

//------------- Event & Interrupt Trigger Module Setup --------------
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
// EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event

//------------------ Trip Zone Digital Compare ----------------------
EPwm1Regs.TZSEL.bit.CBC1 = 0; // 0 TZ1 CBC select
EPwm1Regs.TZSEL.bit.CBC2 = 0; // 1 TZ2 CBC select
EPwm1Regs.TZSEL.bit.CBC3 = 0; // 2 TZ3 CBC select
EPwm1Regs.TZSEL.bit.CBC4 = 0; // 3 TZ4 CBC select
EPwm1Regs.TZSEL.bit.CBC5 = 0; // 4 TZ5 CBC select
EPwm1Regs.TZSEL.bit.CBC6 = 0; // 5 TZ6 CBC select
EPwm1Regs.TZSEL.bit.OSHT1 = 0; // 8 One-shot TZ1 select
EPwm1Regs.TZSEL.bit.OSHT2 = 0; // 9 One-shot TZ2 select
EPwm1Regs.TZSEL.bit.OSHT3 = 0; // 10 One-shot TZ3 select
EPwm1Regs.TZSEL.bit.OSHT4 = 0; // 11 One-shot TZ4 select
EPwm1Regs.TZSEL.bit.OSHT5 = 0; // 12 One-shot TZ5 select
EPwm1Regs.TZSEL.bit.OSHT6 = 0; // 13 One-shot TZ6 select
EPwm1Regs.TZSEL.bit.DCAEVT1 = 0; // 14 One-shot DCAEVT1 select
EPwm1Regs.TZSEL.bit.DCBEVT1 = 0; // 15 One-shot DCBEVT1 select
EPwm1Regs.TZSEL.bit.DCAEVT2 = 0; // 6 DCAEVT2 CBC select
EPwm1Regs.TZSEL.bit.DCBEVT2 = 0; // 7 DCBEVT2 CBC select
}

//========================================================================
// InitEPwm2Example - Initialize EPWM2 configuration
//========================================================================
void Init_EPwm2()
{
//-------------- Simultainous Register Write Linkages ---------------
EPwm2Regs.EPWMXLINK.bit.TBPRDLINK = 1; // TBPRD Link
EPwm2Regs.EPWMXLINK.bit.CMPALINK = 0; // CMP A Link
EPwm2Regs.EPWMXLINK.bit.CMPBLINK = 0; // CMP B Link
EPwm2Regs.EPWMXLINK.bit.CMPCLINK = 0; // CMP C Link
EPwm2Regs.EPWMXLINK.bit.CMPDLINK = 0; // CMP D Link
EPwm2Regs.EPWMXLINK.bit.GLDCTL2LINK = 0; //

/*
//--------------- Global Load Configuration Registers ---------------
EPwm2Regs.GLDCFG.bit.TBPRD_TBPRDHR = 1; // TBPRD
EPwm2Regs.GLDCFG.bit.CMPA_CMPAHR = 1; // Compare A
EPwm2Regs.GLDCFG.bit.CMPB_CMPBHR = 1; // Compare B
EPwm2Regs.GLDCFG.bit.CMPC = 0; // Compare C
EPwm2Regs.GLDCFG.bit.CMPD = 0; // Compare D
EPwm2Regs.GLDCFG.bit.DBCTL = 1; // Dead Band Control
EPwm2Regs.GLDCFG.bit.DBRED_DBREDHR = 1; // DB Rising
EPwm2Regs.GLDCFG.bit.DBFED_DBFEDHR = 1; // DB Falling
EPwm2Regs.GLDCFG.bit.AQCTLA_AQCTLA2 = 0; // AQCTLA/A2
EPwm2Regs.GLDCFG.bit.AQCTLB_AQCTLB2 = 0; // AQCTLB/B2
EPwm2Regs.GLDCFG.bit.AQCSFRC = 0; // AQCSFRC
*/

//------------------- Time Base Register ----------------------------
EPwm2Regs.TBPRD = 0; // Set time Base period
EPwm2Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm2Regs.TBCTR = 0; // Clear counter


//------------------- Time Base Clock -------------------------------
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Counter Mode
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Phase Load Enable
EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP; // Phase Direction Bit
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Active Period Load
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Time Base Clock Pre-scaler
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // SYNC out selection
EPwm2Regs.TBCTL.bit.SWFSYNC = 0; // Software Force Sync Pulse
EPwm2Regs.TBCTL.bit.FREE_SOFT = 0; // Emulation Mode Bits


//------------------- Shadow Register Actions -----------------------
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; //
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; //


//---------------------- Counter Compare ----------------------------
EPwm2Regs.CMPA.bit.CMPA = 2222; // CTR = CMPA
EPwm2Regs.CMPB.bit.CMPB = 2222; // CTR = CMPB
EPwm2Regs.CMPC = 2222; // CTR = CMPC
EPwm2Regs.CMPD = 2222; // CTR = CMPD

//---------------------- Action Qualifiers --------------------------
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A to Zero
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; //
EPwm2Regs.AQCTLB.bit.PRD = AQ_SET; // Set PWM1B to One
EPwm2Regs.AQCTLB.bit.CBD = AQ_CLEAR; //

EPwm2Regs.AQCTLA2.bit.T1U = 0;


//------------------------ Deadband Setup --------------------------
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HI; // Polarity Select Control
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_DISABLE; // Output Mode Control
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; // Input Select Mode Control
EPwm2Regs.DBCTL.bit.LOADREDMODE = 0; // Active DBRED Load Mode
EPwm2Regs.DBCTL.bit.LOADFEDMODE = 0; // Active DBFED Load Mode
EPwm2Regs.DBCTL.bit.SHDWDBREDMODE = 0; // DBRED Block Operating Mode
EPwm2Regs.DBCTL.bit.SHDWDBFEDMODE = 0; // DBFED Block Operating Mode
EPwm2Regs.DBCTL.bit.OUTSWAP = 0; // Output Swap Control
EPwm2Regs.DBCTL.bit.DEDB_MODE = 1; // Dual-Edge B Mode Control
EPwm2Regs.DBCTL.bit.HALFCYCLE = 0; // Half Cycle Clocking Enable

//------------------ Dead Band Timing Values ------------------------
EPwm2Regs.DBRED.bit.DBRED = EPWMx_MIN_DB; // Set Rising edge delay
EPwm2Regs.DBFED.bit.DBFED = EPWMx_MIN_DB; // Set falling edge delay


//------------- Event & Interrupt Trigger Module Setup --------------
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
// EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event


//------------------ Trip Zone Digital Compare ----------------------
EPwm2Regs.TZSEL.bit.CBC1 = 0; // 0 TZ1 CBC select
EPwm2Regs.TZSEL.bit.CBC2 = 0; // 1 TZ2 CBC select
EPwm2Regs.TZSEL.bit.CBC3 = 0; // 2 TZ3 CBC select
EPwm2Regs.TZSEL.bit.CBC4 = 0; // 3 TZ4 CBC select
EPwm2Regs.TZSEL.bit.CBC5 = 0; // 4 TZ5 CBC select
EPwm2Regs.TZSEL.bit.CBC6 = 0; // 5 TZ6 CBC select
EPwm2Regs.TZSEL.bit.OSHT1 = 0; // 8 One-shot TZ1 select
EPwm2Regs.TZSEL.bit.OSHT2 = 0; // 9 One-shot TZ2 select
EPwm2Regs.TZSEL.bit.OSHT3 = 0; // 10 One-shot TZ3 select
EPwm2Regs.TZSEL.bit.OSHT4 = 0; // 11 One-shot TZ4 select
EPwm2Regs.TZSEL.bit.OSHT5 = 0; // 12 One-shot TZ5 select
EPwm2Regs.TZSEL.bit.OSHT6 = 0; // 13 One-shot TZ6 select
EPwm2Regs.TZSEL.bit.DCAEVT1 = 0; // 14 One-shot DCAEVT1 select
EPwm2Regs.TZSEL.bit.DCBEVT1 = 0; // 15 One-shot DCBEVT1 select
EPwm2Regs.TZSEL.bit.DCAEVT2 = 0; // 6 DCAEVT2 CBC select
EPwm2Regs.TZSEL.bit.DCBEVT2 = 0; // 7 DCBEVT2 CBC select
}

//========================================================================
// InitEPwm3Example - Initialize EPWM3 configuration
//========================================================================
void Init_EPwm3()
{
//-------------- Simultanious Register Write Linkages ---------------
EPwm3Regs.EPWMXLINK.bit.TBPRDLINK = 1; // TBPRD Link
EPwm3Regs.EPWMXLINK.bit.CMPALINK = 0; // CMP A Link
EPwm3Regs.EPWMXLINK.bit.CMPBLINK = 0; // CMP B Link
EPwm3Regs.EPWMXLINK.bit.CMPCLINK = 0; // CMP C Link
EPwm3Regs.EPWMXLINK.bit.CMPDLINK = 0; // CMP D Link
EPwm3Regs.EPWMXLINK.bit.GLDCTL2LINK = 0; //

/*
//--------------- Global Load Configuration Registers ---------------
EPwm3Regs.GLDCFG.bit.TBPRD_TBPRDHR = 1; // TBPRD
EPwm3Regs.GLDCFG.bit.CMPA_CMPAHR = 1; // Compare A
EPwm3Regs.GLDCFG.bit.CMPB_CMPBHR = 1; // Compare B
EPwm3Regs.GLDCFG.bit.CMPC = 0; // Compare C
EPwm3Regs.GLDCFG.bit.CMPD = 0; // Compare D
EPwm3Regs.GLDCFG.bit.DBCTL = 1; // Dead Band Control
EPwm3Regs.GLDCFG.bit.DBRED_DBREDHR = 1; // DB Rising
EPwm3Regs.GLDCFG.bit.DBFED_DBFEDHR = 1; // DB Falling
EPwm3Regs.GLDCFG.bit.AQCTLA_AQCTLA2 = 0; // AQCTLA/A2
EPwm3Regs.GLDCFG.bit.AQCTLB_AQCTLB2 = 0; // AQCTLB/B2
EPwm3Regs.GLDCFG.bit.AQCSFRC = 0; // AQCSFRC
*/

//------------------- Time Base Register ----------------------------
EPwm3Regs.TBPRD = 0; // Set time Base period
EPwm3Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm3Regs.TBCTR = 0; // Clear counter


//------------------- Time Base Clock -------------------------------
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Counter Mode
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Phase Load Enable
EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP; // Phase Direction Bit
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Active Period Load
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Time Base Clock Pre-scaler
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // SYNC out selection
EPwm3Regs.TBCTL.bit.SWFSYNC = 0; // Software Force Sync Pulse
EPwm3Regs.TBCTL.bit.FREE_SOFT = 0; // Emulation Mode Bits


//------------------- Shadow Register Actions -----------------------
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; //
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load registers every ZERO
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; //


//---------------------- Counter Compare ----------------------------
EPwm3Regs.CMPA.bit.CMPA = 2222; // CTR = CMPA
EPwm3Regs.CMPB.bit.CMPB = 2222; // CTR = CMPB
EPwm3Regs.CMPC = 2222; // CTR = CMPC
EPwm3Regs.CMPD = 2222; // CTR = CMPD


//---------------------- Action Qualifiers --------------------------
EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A to Zero
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; //
EPwm3Regs.AQCTLB.bit.PRD = AQ_SET; // Set PWM1B to One
EPwm3Regs.AQCTLB.bit.CBD = AQ_CLEAR; //

EPwm3Regs.AQCTLA2.bit.T1U = 0;


//------------- Active Low PWMs - Setup Deadband -------------------
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HI; // Polarity Select Control
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE; // Output Mode Control
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL; // Input Select Mode Control
EPwm3Regs.DBCTL.bit.LOADREDMODE = 0; // Active DBRED Load Mode
EPwm3Regs.DBCTL.bit.LOADFEDMODE = 0; // Active DBFED Load Mode
EPwm3Regs.DBCTL.bit.SHDWDBREDMODE = 0; // DBRED Block Operating Mode
EPwm3Regs.DBCTL.bit.SHDWDBFEDMODE = 0; // DBFED Block Operating Mode
EPwm3Regs.DBCTL.bit.OUTSWAP = 0; // Output Swap Control
EPwm3Regs.DBCTL.bit.DEDB_MODE = 0; // Dual-Edge B Mode Control
EPwm3Regs.DBCTL.bit.HALFCYCLE = 0; // Half Cycle Clocking Enable

//------------------ Dead Band Timing Values ------------------------
EPwm3Regs.DBRED.bit.DBRED = EPWMx_MIN_DB; // Set Rising edge delay
EPwm3Regs.DBFED.bit.DBFED = EPWMx_MIN_DB; // Set falling edge delay


//------------ Interrupt where we will change the Deadband --------------
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
// EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event


//------------------ Trip Zone Digital Compare ----------------------
EPwm3Regs.TZSEL.bit.CBC1 = 0; // 0 TZ1 CBC select
EPwm3Regs.TZSEL.bit.CBC2 = 0; // 1 TZ2 CBC select
EPwm3Regs.TZSEL.bit.CBC3 = 0; // 2 TZ3 CBC select
EPwm3Regs.TZSEL.bit.CBC4 = 0; // 3 TZ4 CBC select
EPwm3Regs.TZSEL.bit.CBC5 = 0; // 4 TZ5 CBC select
EPwm3Regs.TZSEL.bit.CBC6 = 0; // 5 TZ6 CBC select
EPwm3Regs.TZSEL.bit.OSHT1 = 0; // 8 One-shot TZ1 select
EPwm3Regs.TZSEL.bit.OSHT2 = 0; // 9 One-shot TZ2 select
EPwm3Regs.TZSEL.bit.OSHT3 = 0; // 10 One-shot TZ3 select
EPwm3Regs.TZSEL.bit.OSHT4 = 0; // 11 One-shot TZ4 select
EPwm3Regs.TZSEL.bit.OSHT5 = 0; // 12 One-shot TZ5 select
EPwm3Regs.TZSEL.bit.OSHT6 = 0; // 13 One-shot TZ6 select
EPwm3Regs.TZSEL.bit.DCAEVT1 = 0; // 14 One-shot DCAEVT1 select
EPwm3Regs.TZSEL.bit.DCBEVT1 = 0; // 15 One-shot DCBEVT1 select
EPwm3Regs.TZSEL.bit.DCAEVT2 = 0; // 6 DCAEVT2 CBC select
EPwm3Regs.TZSEL.bit.DCBEVT2 = 0; // 7 DCBEVT2 CBC select
}


//========================================================================
// InitEPwm4Example - Initialize EPWM4 configuration
//========================================================================
void Init_EPwm4()
{
//-------------- Simultanious Register Write Linkages ---------------
EPwm4Regs.EPWMXLINK.bit.TBPRDLINK = 1; // TBPRD Link
EPwm4Regs.EPWMXLINK.bit.CMPALINK = 0; // CMP A Link
EPwm4Regs.EPWMXLINK.bit.CMPBLINK = 0; // CMP B Link
EPwm4Regs.EPWMXLINK.bit.CMPCLINK = 0; // CMP C Link
EPwm4Regs.EPWMXLINK.bit.CMPDLINK = 0; // CMP D Link
EPwm4Regs.EPWMXLINK.bit.GLDCTL2LINK = 0; //


//--------------- Global Load Configuration Registers ---------------
EPwm4Regs.GLDCFG.bit.TBPRD_TBPRDHR = 1; // TBPRD
EPwm4Regs.GLDCFG.bit.CMPA_CMPAHR = 1; // Compare A
EPwm4Regs.GLDCFG.bit.CMPB_CMPBHR = 1; // Compare B
EPwm4Regs.GLDCFG.bit.CMPC = 0; // Compare C
EPwm4Regs.GLDCFG.bit.CMPD = 0; // Compare D
EPwm4Regs.GLDCFG.bit.DBCTL = 1; // Dead Band Control
EPwm4Regs.GLDCFG.bit.DBRED_DBREDHR = 1; // DB Rising
EPwm4Regs.GLDCFG.bit.DBFED_DBFEDHR = 1; // DB Falling
EPwm4Regs.GLDCFG.bit.AQCTLA_AQCTLA2 = 0; // AQCTLA/A2
EPwm4Regs.GLDCFG.bit.AQCTLB_AQCTLB2 = 0; // AQCTLB/B2
EPwm4Regs.GLDCFG.bit.AQCSFRC = 0; // AQCSFRC


//------------------- Time Base Register ----------------------------
EPwm4Regs.TBPRD = 0; // Set time Base period
EPwm4Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm4Regs.TBCTR = 0; // Clear counter


//------------------- Time Base Clock -------------------------------
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Counter Mode
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Phase Load Enable
EPwm4Regs.TBCTL.bit.PHSDIR = TB_UP; // Phase Direction Bit
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Active Period Load
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Time Base Clock Pre-scaler
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // SYNC out selection
EPwm4Regs.TBCTL.bit.SWFSYNC = 0; // Software Force Sync Pulse
EPwm4Regs.TBCTL.bit.FREE_SOFT = 0; // Emulation Mode Bits

//------------------- Shadow Register Actions -----------------------
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; //
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load registers every ZERO
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; //

//---------------------- Counter Compare ----------------------------
EPwm4Regs.CMPA.bit.CMPA = 2222; // CTR = CMPA
EPwm4Regs.CMPB.bit.CMPB = 2222; // CTR = CMPB
EPwm4Regs.CMPC = 2222; // CTR = CMPC
EPwm4Regs.CMPD = 2222; // CTR = CMPD

//---------------------- Action Qualifiers --------------------------
EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A to Zero
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; //
EPwm4Regs.AQCTLB.bit.PRD = AQ_SET; // Set PWM1B to One
EPwm4Regs.AQCTLB.bit.CBD = AQ_CLEAR; //

//------------- Active Low PWMs - Setup Deadband -------------------
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HI; // Polarity Select Control
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_DISABLE; // Output Mode Control
EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL; // Input Select Mode Control
EPwm4Regs.DBCTL.bit.LOADREDMODE = 0; // Active DBRED Load Mode
EPwm4Regs.DBCTL.bit.LOADFEDMODE = 0; // Active DBFED Load Mode
EPwm4Regs.DBCTL.bit.SHDWDBREDMODE = 0; // DBRED Block Operating Mode
EPwm4Regs.DBCTL.bit.SHDWDBFEDMODE = 0; // DBFED Block Operating Mode
EPwm4Regs.DBCTL.bit.OUTSWAP = 0; // Output Swap Control
EPwm4Regs.DBCTL.bit.DEDB_MODE = 0; // Dual-Edge B Mode Control
EPwm4Regs.DBCTL.bit.HALFCYCLE = 0; // Half Cycle Clocking Enable

//------------------ Dead Band Timing Values ------------------------
EPwm4Regs.DBRED.bit.DBRED = EPWMx_MIN_DB; // Set Rising edge delay
EPwm4Regs.DBFED.bit.DBFED = EPWMx_MIN_DB; // Set falling edge delay

//------------ Interrupt where we will change the Deadband --------------
EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
// EPwm4Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm4Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event


//------------------ Trip Zone Digital Compare ----------------------
EPwm4Regs.TZSEL.bit.CBC1 = 0; // 0 TZ1 CBC select
EPwm4Regs.TZSEL.bit.CBC2 = 0; // 1 TZ2 CBC select
EPwm4Regs.TZSEL.bit.CBC3 = 0; // 2 TZ3 CBC select
EPwm4Regs.TZSEL.bit.CBC4 = 0; // 3 TZ4 CBC select
EPwm4Regs.TZSEL.bit.CBC5 = 0; // 4 TZ5 CBC select
EPwm4Regs.TZSEL.bit.CBC6 = 0; // 5 TZ6 CBC select
EPwm4Regs.TZSEL.bit.OSHT1 = 0; // 8 One-shot TZ1 select
EPwm4Regs.TZSEL.bit.OSHT2 = 0; // 9 One-shot TZ2 select
EPwm4Regs.TZSEL.bit.OSHT3 = 0; // 10 One-shot TZ3 select
EPwm4Regs.TZSEL.bit.OSHT4 = 0; // 11 One-shot TZ4 select
EPwm4Regs.TZSEL.bit.OSHT5 = 0; // 12 One-shot TZ5 select
EPwm4Regs.TZSEL.bit.OSHT6 = 0; // 13 One-shot TZ6 select
EPwm4Regs.TZSEL.bit.DCAEVT1 = 0; // 14 One-shot DCAEVT1 select
EPwm4Regs.TZSEL.bit.DCBEVT1 = 0; // 15 One-shot DCBEVT1 select
EPwm4Regs.TZSEL.bit.DCAEVT2 = 0; // 6 DCAEVT2 CBC select
EPwm4Regs.TZSEL.bit.DCBEVT2 = 0; // 7 DCBEVT2 CBC select
}

//========================================================================
// InitEPwm2Example - Initialize EPWM2 configuration
//========================================================================
void Init_EPwm5()
{
//-------------- Simultainous Register Write Linkages ---------------
EPwm5Regs.EPWMXLINK.bit.TBPRDLINK = 0; // TBPRD Link
EPwm5Regs.EPWMXLINK.bit.CMPALINK = 0; // CMP A Link
EPwm5Regs.EPWMXLINK.bit.CMPBLINK = 0; // CMP B Link
EPwm5Regs.EPWMXLINK.bit.CMPCLINK = 0; // CMP C Link
EPwm5Regs.EPWMXLINK.bit.CMPDLINK = 0; // CMP D Link
EPwm5Regs.EPWMXLINK.bit.GLDCTL2LINK = 0; //

/*
//--------------- Global Load Configuration Registers ---------------
EPwm5Regs.GLDCFG.bit.TBPRD_TBPRDHR = 1; // TBPRD
EPwm5Regs.GLDCFG.bit.CMPA_CMPAHR = 1; // Compare A
EPwm5Regs.GLDCFG.bit.CMPB_CMPBHR = 1; // Compare B
EPwm5Regs.GLDCFG.bit.CMPC = 0; // Compare C
EPwm5Regs.GLDCFG.bit.CMPD = 0; // Compare D
EPwm5Regs.GLDCFG.bit.DBCTL = 1; // Dead Band Control
EPwm5Regs.GLDCFG.bit.DBRED_DBREDHR = 1; // DB Rising
EPwm5Regs.GLDCFG.bit.DBFED_DBFEDHR = 1; // DB Falling
EPwm5Regs.GLDCFG.bit.AQCTLA_AQCTLA2 = 0; // AQCTLA/A2
EPwm5Regs.GLDCFG.bit.AQCTLB_AQCTLB2 = 0; // AQCTLB/B2
EPwm5Regs.GLDCFG.bit.AQCSFRC = 0; // AQCSFRC
*/

//------------------- Time Base Register ----------------------------
EPwm5Regs.TBPRD = 0; // Set time Base period
EPwm5Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm5Regs.TBCTR = 0; // Clear counter


//------------------- Time Base Clock -------------------------------
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Counter Mode
EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Phase Load Enable
EPwm5Regs.TBCTL.bit.PHSDIR = TB_UP; // Phase Direction Bit
EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Active Period Load
EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Time Base Clock Pre-scaler
EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // SYNC out selection
EPwm5Regs.TBCTL.bit.SWFSYNC = 0; // Software Force Sync Pulse
EPwm5Regs.TBCTL.bit.FREE_SOFT = 0; // Emulation Mode Bits


//------------------- Shadow Register Actions -----------------------
EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //
EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; //
EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load registers every ZERO
EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; //


//---------------------- Counter Compare ----------------------------
EPwm5Regs.CMPA.bit.CMPA = 2222; // CTR = CMPA
EPwm5Regs.CMPB.bit.CMPB = 2222; // CTR = CMPB
EPwm5Regs.CMPC = 2222; // CTR = CMPC
EPwm5Regs.CMPD = 2222; // CTR = CMPD

//---------------------- Action Qualifiers --------------------------
EPwm5Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A to Zero
EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR; //
EPwm5Regs.AQCTLB.bit.PRD = AQ_SET; // Set PWM1B to One
EPwm5Regs.AQCTLB.bit.CBD = AQ_CLEAR; //

EPwm5Regs.AQCTLA2.bit.T1U = 0;


//------------- Active Low PWMs - Setup Deadband -------------------
EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HI; // Polarity Select Control
EPwm5Regs.DBCTL.bit.OUT_MODE = DB_DISABLE; // Output Mode Control
EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL; // Input Select Mode Control
EPwm5Regs.DBCTL.bit.LOADREDMODE = 0; // Active DBRED Load Mode
EPwm5Regs.DBCTL.bit.LOADFEDMODE = 0; // Active DBFED Load Mode
EPwm5Regs.DBCTL.bit.SHDWDBREDMODE = 0; // DBRED Block Operating Mode
EPwm5Regs.DBCTL.bit.SHDWDBFEDMODE = 0; // DBFED Block Operating Mode
EPwm5Regs.DBCTL.bit.OUTSWAP = 0; // Output Swap Control
EPwm5Regs.DBCTL.bit.DEDB_MODE = 0; // Dual-Edge B Mode Control
EPwm5Regs.DBCTL.bit.HALFCYCLE = 0; // Half Cycle Clocking Enable

//------------------ Dead Band Timing Values ------------------------
EPwm5Regs.DBRED.bit.DBRED = EPWMx_MIN_DB; // Set Rising edge delay
EPwm5Regs.DBFED.bit.DBFED = EPWMx_MIN_DB; // Set falling edge delay


//------------ Interrupt where we will change the Deadband --------------
EPwm5Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
// EPwm5Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm5Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event


//------------------ Trip Zone Digital Compare ----------------------
EPwm5Regs.TZSEL.bit.CBC1 = 0; // 0 TZ1 CBC select
EPwm5Regs.TZSEL.bit.CBC2 = 0; // 1 TZ2 CBC select
EPwm5Regs.TZSEL.bit.CBC3 = 0; // 2 TZ3 CBC select
EPwm5Regs.TZSEL.bit.CBC4 = 0; // 3 TZ4 CBC select
EPwm5Regs.TZSEL.bit.CBC5 = 0; // 4 TZ5 CBC select
EPwm5Regs.TZSEL.bit.CBC6 = 0; // 5 TZ6 CBC select
EPwm5Regs.TZSEL.bit.OSHT1 = 0; // 8 One-shot TZ1 select
EPwm5Regs.TZSEL.bit.OSHT2 = 0; // 9 One-shot TZ2 select
EPwm5Regs.TZSEL.bit.OSHT3 = 0; // 10 One-shot TZ3 select
EPwm5Regs.TZSEL.bit.OSHT4 = 0; // 11 One-shot TZ4 select
EPwm5Regs.TZSEL.bit.OSHT5 = 0; // 12 One-shot TZ5 select
EPwm5Regs.TZSEL.bit.OSHT6 = 0; // 13 One-shot TZ6 select
EPwm5Regs.TZSEL.bit.DCAEVT1 = 0; // 14 One-shot DCAEVT1 select
EPwm5Regs.TZSEL.bit.DCBEVT1 = 0; // 15 One-shot DCBEVT1 select
EPwm5Regs.TZSEL.bit.DCAEVT2 = 0; // 6 DCAEVT2 CBC select
EPwm5Regs.TZSEL.bit.DCBEVT2 = 0; // 7 DCBEVT2 CBC select
}

//========================================================================
// InitEPwm2Example - Initialize EPWM2 configuration
//========================================================================
void Init_EPwm6()
{
//-------------- Simultainous Register Write Linkages ---------------
EPwm6Regs.EPWMXLINK.bit.TBPRDLINK = 0; // TBPRD Link
EPwm6Regs.EPWMXLINK.bit.CMPALINK = 0; // CMP A Link
EPwm6Regs.EPWMXLINK.bit.CMPBLINK = 0; // CMP B Link
EPwm6Regs.EPWMXLINK.bit.CMPCLINK = 0; // CMP C Link
EPwm6Regs.EPWMXLINK.bit.CMPDLINK = 0; // CMP D Link
EPwm6Regs.EPWMXLINK.bit.GLDCTL2LINK = 0; //

/*
//--------------- Global Load Configuration Registers ---------------
EPwm6Regs.GLDCFG.bit.TBPRD_TBPRDHR = 1; // TBPRD
EPwm6Regs.GLDCFG.bit.CMPA_CMPAHR = 1; // Compare A
EPwm6Regs.GLDCFG.bit.CMPB_CMPBHR = 1; // Compare B
EPwm6Regs.GLDCFG.bit.CMPC = 0; // Compare C
EPwm6Regs.GLDCFG.bit.CMPD = 0; // Compare D
EPwm6Regs.GLDCFG.bit.DBCTL = 1; // Dead Band Control
EPwm6Regs.GLDCFG.bit.DBRED_DBREDHR = 1; // DB Rising
EPwm6Regs.GLDCFG.bit.DBFED_DBFEDHR = 1; // DB Falling
EPwm6Regs.GLDCFG.bit.AQCTLA_AQCTLA2 = 0; // AQCTLA/A2
EPwm6Regs.GLDCFG.bit.AQCTLB_AQCTLB2 = 0; // AQCTLB/B2
EPwm6Regs.GLDCFG.bit.AQCSFRC = 0; // AQCSFRC
*/

//------------------- Time Base Register ----------------------------
EPwm6Regs.TBPRD = 0; // Set time Base period
EPwm6Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm6Regs.TBCTR = 0; // Clear counter


//------------------- Time Base Clock -------------------------------
EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Counter Mode
EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Phase Load Enable
EPwm6Regs.TBCTL.bit.PHSDIR = TB_UP; // Phase Direction Bit
EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Active Period Load
EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Time Base Clock Pre-scaler
EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // SYNC out selection
EPwm6Regs.TBCTL.bit.SWFSYNC = 0; // Software Force Sync Pulse
EPwm6Regs.TBCTL.bit.FREE_SOFT = 0; // Emulation Mode Bits


//------------------- Shadow Register Actions -----------------------
EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //
EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; //
EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load registers every ZERO
EPwm6Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; //


//---------------------- Counter Compare ----------------------------
EPwm6Regs.CMPA.bit.CMPA = 2222; // CTR = CMPA
EPwm6Regs.CMPB.bit.CMPB = 2222; // CTR = CMPB
EPwm6Regs.CMPC = 2222; // CTR = CMPC
EPwm6Regs.CMPD = 2222; // CTR = CMPD

//---------------------- Action Qualifiers --------------------------
EPwm6Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A to Zero
EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR; //
EPwm6Regs.AQCTLB.bit.PRD = AQ_SET; // Set PWM1B to One
EPwm6Regs.AQCTLB.bit.CBD = AQ_CLEAR; //

EPwm6Regs.AQCTLA2.bit.T1U = 0;


//------------- Active Low PWMs - Setup Deadband -------------------
EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HI; // Polarity Select Control
EPwm6Regs.DBCTL.bit.OUT_MODE = DB_DISABLE; // Output Mode Control
EPwm6Regs.DBCTL.bit.IN_MODE = DBA_ALL; // Input Select Mode Control
EPwm6Regs.DBCTL.bit.LOADREDMODE = 0; // Active DBRED Load Mode
EPwm6Regs.DBCTL.bit.LOADFEDMODE = 0; // Active DBFED Load Mode
EPwm6Regs.DBCTL.bit.SHDWDBREDMODE = 0; // DBRED Block Operating Mode
EPwm6Regs.DBCTL.bit.SHDWDBFEDMODE = 0; // DBFED Block Operating Mode
EPwm6Regs.DBCTL.bit.OUTSWAP = 0; // Output Swap Control
EPwm6Regs.DBCTL.bit.DEDB_MODE = 0; // Dual-Edge B Mode Control
EPwm6Regs.DBCTL.bit.HALFCYCLE = 0; // Half Cycle Clocking Enable

//------------------ Dead Band Timing Values ------------------------
EPwm6Regs.DBRED.bit.DBRED = EPWMx_MIN_DB; // Set Rising edge delay
EPwm6Regs.DBFED.bit.DBFED = EPWMx_MIN_DB; // Set falling edge delay


//------------ Interrupt where we will change the Deadband --------------
EPwm6Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
// EPwm6Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm6Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event


//------------------ Trip Zone Digital Compare ----------------------
EPwm6Regs.TZSEL.bit.CBC1 = 0; // 0 TZ1 CBC select
EPwm6Regs.TZSEL.bit.CBC2 = 0; // 1 TZ2 CBC select
EPwm6Regs.TZSEL.bit.CBC3 = 0; // 2 TZ3 CBC select
EPwm6Regs.TZSEL.bit.CBC4 = 0; // 3 TZ4 CBC select
EPwm6Regs.TZSEL.bit.CBC5 = 0; // 4 TZ5 CBC select
EPwm6Regs.TZSEL.bit.CBC6 = 0; // 5 TZ6 CBC select
EPwm6Regs.TZSEL.bit.OSHT1 = 0; // 8 One-shot TZ1 select
EPwm6Regs.TZSEL.bit.OSHT2 = 0; // 9 One-shot TZ2 select
EPwm6Regs.TZSEL.bit.OSHT3 = 0; // 10 One-shot TZ3 select
EPwm6Regs.TZSEL.bit.OSHT4 = 0; // 11 One-shot TZ4 select
EPwm6Regs.TZSEL.bit.OSHT5 = 0; // 12 One-shot TZ5 select
EPwm6Regs.TZSEL.bit.OSHT6 = 0; // 13 One-shot TZ6 select
EPwm6Regs.TZSEL.bit.DCAEVT1 = 0; // 14 One-shot DCAEVT1 select
EPwm6Regs.TZSEL.bit.DCBEVT1 = 0; // 15 One-shot DCBEVT1 select
EPwm6Regs.TZSEL.bit.DCAEVT2 = 0; // 6 DCAEVT2 CBC select
EPwm6Regs.TZSEL.bit.DCBEVT2 = 0; // 7 DCBEVT2 CBC select
}

//========================================================================
// InitEPwm2Example - Initialize EPWM2 configuration
//========================================================================
void Init_EPwm7()
{
//-------------- Simultainous Register Write Linkages ---------------
EPwm7Regs.EPWMXLINK.bit.TBPRDLINK = 0; // TBPRD Link
EPwm7Regs.EPWMXLINK.bit.CMPALINK = 0; // CMP A Link
EPwm7Regs.EPWMXLINK.bit.CMPBLINK = 0; // CMP B Link
EPwm7Regs.EPWMXLINK.bit.CMPCLINK = 0; // CMP C Link
EPwm7Regs.EPWMXLINK.bit.CMPDLINK = 0; // CMP D Link
EPwm7Regs.EPWMXLINK.bit.GLDCTL2LINK = 0; //

/*
//--------------- Global Load Configuration Registers ---------------
EPwm7Regs.GLDCFG.bit.TBPRD_TBPRDHR = 1; // TBPRD
EPwm7Regs.GLDCFG.bit.CMPA_CMPAHR = 1; // Compare A
EPwm7Regs.GLDCFG.bit.CMPB_CMPBHR = 1; // Compare B
EPwm7Regs.GLDCFG.bit.CMPC = 0; // Compare C
EPwm7Regs.GLDCFG.bit.CMPD = 0; // Compare D
EPwm7Regs.GLDCFG.bit.DBCTL = 1; // Dead Band Control
EPwm7Regs.GLDCFG.bit.DBRED_DBREDHR = 1; // DB Rising
EPwm7Regs.GLDCFG.bit.DBFED_DBFEDHR = 1; // DB Falling
EPwm7Regs.GLDCFG.bit.AQCTLA_AQCTLA2 = 0; // AQCTLA/A2
EPwm7Regs.GLDCFG.bit.AQCTLB_AQCTLB2 = 0; // AQCTLB/B2
EPwm7Regs.GLDCFG.bit.AQCSFRC = 0; // AQCSFRC
*/

//------------------- Time Base Register ----------------------------
EPwm7Regs.TBPRD = 0; // Set time Base period
EPwm7Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm7Regs.TBCTR = 0; // Clear counter


//------------------- Time Base Clock -------------------------------
EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Counter Mode
EPwm7Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Phase Load Enable
EPwm7Regs.TBCTL.bit.PHSDIR = TB_UP; // Phase Direction Bit
EPwm7Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Active Period Load
EPwm7Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm7Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Time Base Clock Pre-scaler
EPwm7Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // SYNC out selection
EPwm7Regs.TBCTL.bit.SWFSYNC = 0; // Software Force Sync Pulse
EPwm7Regs.TBCTL.bit.FREE_SOFT = 0; // Emulation Mode Bits


//------------------- Shadow Register Actions -----------------------
EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //
EPwm7Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; //
EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load registers every ZERO
EPwm7Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; //


//---------------------- Counter Compare ----------------------------
EPwm7Regs.CMPA.bit.CMPA = 2222; // CTR = CMPA
EPwm7Regs.CMPB.bit.CMPB = 2222; // CTR = CMPB
EPwm7Regs.CMPC = 2222; // CTR = CMPC
EPwm7Regs.CMPD = 2222; // CTR = CMPD

//---------------------- Action Qualifiers --------------------------
EPwm7Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A to Zero
EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR; //
EPwm7Regs.AQCTLB.bit.PRD = AQ_SET; // Set PWM1B to One
EPwm7Regs.AQCTLB.bit.CBD = AQ_CLEAR; //

EPwm7Regs.AQCTLA2.bit.T1U = 0;


//------------- Active Low PWMs - Setup Deadband -------------------
EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HI; // Polarity Select Control
EPwm7Regs.DBCTL.bit.OUT_MODE = DB_DISABLE; // Output Mode Control
EPwm7Regs.DBCTL.bit.IN_MODE = DBA_ALL; // Input Select Mode Control
EPwm7Regs.DBCTL.bit.LOADREDMODE = 0; // Active DBRED Load Mode
EPwm7Regs.DBCTL.bit.LOADFEDMODE = 0; // Active DBFED Load Mode
EPwm7Regs.DBCTL.bit.SHDWDBREDMODE = 0; // DBRED Block Operating Mode
EPwm7Regs.DBCTL.bit.SHDWDBFEDMODE = 0; // DBFED Block Operating Mode
EPwm7Regs.DBCTL.bit.OUTSWAP = 0; // Output Swap Control
EPwm7Regs.DBCTL.bit.DEDB_MODE = 0; // Dual-Edge B Mode Control
EPwm7Regs.DBCTL.bit.HALFCYCLE = 0; // Half Cycle Clocking Enable

//------------------ Dead Band Timing Values ------------------------
EPwm7Regs.DBRED.bit.DBRED = EPWMx_MIN_DB; // Set Rising edge delay
EPwm7Regs.DBFED.bit.DBFED = EPWMx_MIN_DB; // Set falling edge delay


//------------ Interrupt where we will change the Deadband --------------
EPwm7Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
// EPwm7Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm7Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event


//------------------ Trip Zone Digital Compare ----------------------
EPwm7Regs.TZSEL.bit.CBC1 = 0; // 0 TZ1 CBC select
EPwm7Regs.TZSEL.bit.CBC2 = 0; // 1 TZ2 CBC select
EPwm7Regs.TZSEL.bit.CBC3 = 0; // 2 TZ3 CBC select
EPwm7Regs.TZSEL.bit.CBC4 = 0; // 3 TZ4 CBC select
EPwm7Regs.TZSEL.bit.CBC5 = 0; // 4 TZ5 CBC select
EPwm7Regs.TZSEL.bit.CBC6 = 0; // 5 TZ6 CBC select
EPwm7Regs.TZSEL.bit.OSHT1 = 0; // 8 One-shot TZ1 select
EPwm7Regs.TZSEL.bit.OSHT2 = 0; // 9 One-shot TZ2 select
EPwm7Regs.TZSEL.bit.OSHT3 = 0; // 10 One-shot TZ3 select
EPwm7Regs.TZSEL.bit.OSHT4 = 0; // 11 One-shot TZ4 select
EPwm7Regs.TZSEL.bit.OSHT5 = 0; // 12 One-shot TZ5 select
EPwm7Regs.TZSEL.bit.OSHT6 = 0; // 13 One-shot TZ6 select
EPwm7Regs.TZSEL.bit.DCAEVT1 = 0; // 14 One-shot DCAEVT1 select
EPwm7Regs.TZSEL.bit.DCBEVT1 = 0; // 15 One-shot DCBEVT1 select
EPwm7Regs.TZSEL.bit.DCAEVT2 = 0; // 6 DCAEVT2 CBC select
EPwm7Regs.TZSEL.bit.DCBEVT2 = 0; // 7 DCBEVT2 CBC select
}

//========================================================================
// InitEPwm2Example - Initialize EPWM2 configuration
//========================================================================
void Init_EPwm8()
{
//-------------- Simultainous Register Write Linkages ---------------
EPwm8Regs.EPWMXLINK.bit.TBPRDLINK = 0; // TBPRD Link
EPwm8Regs.EPWMXLINK.bit.CMPALINK = 0; // CMP A Link
EPwm8Regs.EPWMXLINK.bit.CMPBLINK = 0; // CMP B Link
EPwm8Regs.EPWMXLINK.bit.CMPCLINK = 0; // CMP C Link
EPwm8Regs.EPWMXLINK.bit.CMPDLINK = 0; // CMP D Link
EPwm8Regs.EPWMXLINK.bit.GLDCTL2LINK = 0; //

/*
//--------------- Global Load Configuration Registers ---------------
EPwm8Regs.GLDCFG.bit.TBPRD_TBPRDHR = 1; // TBPRD
EPwm8Regs.GLDCFG.bit.CMPA_CMPAHR = 1; // Compare A
EPwm8Regs.GLDCFG.bit.CMPB_CMPBHR = 1; // Compare B
EPwm8Regs.GLDCFG.bit.CMPC = 0; // Compare C
EPwm8Regs.GLDCFG.bit.CMPD = 0; // Compare D
EPwm8Regs.GLDCFG.bit.DBCTL = 1; // Dead Band Control
EPwm8Regs.GLDCFG.bit.DBRED_DBREDHR = 1; // DB Rising
EPwm8Regs.GLDCFG.bit.DBFED_DBFEDHR = 1; // DB Falling
EPwm8Regs.GLDCFG.bit.AQCTLA_AQCTLA2 = 0; // AQCTLA/A2
EPwm8Regs.GLDCFG.bit.AQCTLB_AQCTLB2 = 0; // AQCTLB/B2
EPwm8Regs.GLDCFG.bit.AQCSFRC = 0; // AQCSFRC
*/

//------------------- Time Base Register ----------------------------
EPwm8Regs.TBPRD = 0; // Set time Base period
EPwm8Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm8Regs.TBCTR = 0; // Clear counter


//------------------- Time Base Clock -------------------------------
EPwm8Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Counter Mode
EPwm8Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Phase Load Enable
EPwm8Regs.TBCTL.bit.PHSDIR = TB_UP; // Phase Direction Bit
EPwm8Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Active Period Load
EPwm8Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm8Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Time Base Clock Pre-scaler
EPwm8Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // SYNC out selection
EPwm8Regs.TBCTL.bit.SWFSYNC = 0; // Software Force Sync Pulse
EPwm8Regs.TBCTL.bit.FREE_SOFT = 0; // Emulation Mode Bits


//------------------- Shadow Register Actions -----------------------
EPwm8Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; //
EPwm8Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; //
EPwm8Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load registers every ZERO
EPwm8Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; //


//---------------------- Counter Compare ----------------------------
EPwm8Regs.CMPA.bit.CMPA = 2222; // CTR = CMPA
EPwm8Regs.CMPB.bit.CMPB = 2222; // CTR = CMPB
EPwm8Regs.CMPC = 2222; // CTR = CMPC
EPwm8Regs.CMPD = 2222; // CTR = CMPD

//---------------------- Action Qualifiers --------------------------
EPwm8Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A to Zero
EPwm8Regs.AQCTLA.bit.CAU = AQ_CLEAR; //
EPwm8Regs.AQCTLB.bit.PRD = AQ_SET; // Set PWM1B to One
EPwm8Regs.AQCTLB.bit.CBD = AQ_CLEAR; //

EPwm8Regs.AQCTLA2.bit.T1U = 0;


//------------- Active Low PWMs - Setup Deadband -------------------
EPwm8Regs.DBCTL.bit.POLSEL = DB_ACTV_HI; // Polarity Select Control
EPwm8Regs.DBCTL.bit.OUT_MODE = DB_DISABLE; // Output Mode Control
EPwm8Regs.DBCTL.bit.IN_MODE = DBA_ALL; // Input Select Mode Control
EPwm8Regs.DBCTL.bit.LOADREDMODE = 0; // Active DBRED Load Mode
EPwm8Regs.DBCTL.bit.LOADFEDMODE = 0; // Active DBFED Load Mode
EPwm8Regs.DBCTL.bit.SHDWDBREDMODE = 0; // DBRED Block Operating Mode
EPwm8Regs.DBCTL.bit.SHDWDBFEDMODE = 0; // DBFED Block Operating Mode
EPwm8Regs.DBCTL.bit.OUTSWAP = 0; // Output Swap Control
EPwm8Regs.DBCTL.bit.DEDB_MODE = 0; // Dual-Edge B Mode Control
EPwm8Regs.DBCTL.bit.HALFCYCLE = 0; // Half Cycle Clocking Enable

//------------------ Dead Band Timing Values ------------------------
EPwm8Regs.DBRED.bit.DBRED = EPWMx_MIN_DB; // Set Rising edge delay
EPwm8Regs.DBFED.bit.DBFED = EPWMx_MIN_DB; // Set falling edge delay


//------------ Interrupt where we will change the Deadband --------------
EPwm8Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
// EPwm8Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm8Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event


//------------------ Trip Zone Digital Compare ----------------------
EPwm8Regs.TZSEL.bit.CBC1 = 0; // 0 TZ1 CBC select
EPwm8Regs.TZSEL.bit.CBC2 = 0; // 1 TZ2 CBC select
EPwm8Regs.TZSEL.bit.CBC3 = 0; // 2 TZ3 CBC select
EPwm8Regs.TZSEL.bit.CBC4 = 0; // 3 TZ4 CBC select
EPwm8Regs.TZSEL.bit.CBC5 = 0; // 4 TZ5 CBC select
EPwm8Regs.TZSEL.bit.CBC6 = 0; // 5 TZ6 CBC select
EPwm8Regs.TZSEL.bit.OSHT1 = 0; // 8 One-shot TZ1 select
EPwm8Regs.TZSEL.bit.OSHT2 = 0; // 9 One-shot TZ2 select
EPwm8Regs.TZSEL.bit.OSHT3 = 0; // 10 One-shot TZ3 select
EPwm8Regs.TZSEL.bit.OSHT4 = 0; // 11 One-shot TZ4 select
EPwm8Regs.TZSEL.bit.OSHT5 = 0; // 12 One-shot TZ5 select
EPwm8Regs.TZSEL.bit.OSHT6 = 0; // 13 One-shot TZ6 select
EPwm8Regs.TZSEL.bit.DCAEVT1 = 0; // 14 One-shot DCAEVT1 select
EPwm8Regs.TZSEL.bit.DCBEVT1 = 0; // 15 One-shot DCBEVT1 select
EPwm8Regs.TZSEL.bit.DCAEVT2 = 0; // 6 DCAEVT2 CBC select
EPwm8Regs.TZSEL.bit.DCBEVT2 = 0; // 7 DCBEVT2 CBC select
}


//========================================================================
// Init System
//========================================================================
void Init_System()
{


//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xS_SysCtrl.c file.
//
InitSysCtrl();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xS_Gpio.c file and
// illustrates how to set the GPIO to its default state.
//
InitGpio();
GPIO_SetupPinMux(31, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(31, GPIO_OUTPUT, GPIO_PUSHPULL);

GPIO_SetupPinMux(34, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(34, GPIO_OUTPUT, GPIO_PUSHPULL);

//
// enable PWM1, PWM2, PWM3, PWM4
//
CpuSysRegs.PCLKCR2.bit.EPWM1=1;
CpuSysRegs.PCLKCR2.bit.EPWM2=1;
CpuSysRegs.PCLKCR2.bit.EPWM3=1;
CpuSysRegs.PCLKCR2.bit.EPWM4=1;
CpuSysRegs.PCLKCR2.bit.EPWM5=1;
CpuSysRegs.PCLKCR2.bit.EPWM6=1;
CpuSysRegs.PCLKCR2.bit.EPWM7=1;
CpuSysRegs.PCLKCR2.bit.EPWM8=1;

//
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the F2837xS_EPwm.c file
//
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
InitEPwm5Gpio();
InitEPwm6Gpio();
InitEPwm7Gpio();
InitEPwm8Gpio();

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
DINT;

//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xS_PieCtrl.c file.
//
InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2837xS_DefaultIsr.c.
// This function is found in F2837xS_PieVect.c.
//
InitPieVectTable();

//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM1_INT = &epwm1_isr;
PieVectTable.EPWM2_INT = &epwm2_isr;
PieVectTable.EPWM3_INT = &epwm3_isr;
PieVectTable.EPWM4_INT = &epwm4_isr;
PieVectTable.EPWM4_INT = &epwm5_isr;
PieVectTable.EPWM4_INT = &epwm6_isr;
PieVectTable.EPWM4_INT = &epwm7_isr;
PieVectTable.EPWM4_INT = &epwm8_isr;
EDIS; // This is needed to disable write to EALLOW protected registers

//
// Step 4. Initialize the Device Peripherals:
//
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
EDIS;

Init_EPwm1(); //
Init_EPwm2();
Init_EPwm3();
Init_EPwm4();
Init_EPwm5();
Init_EPwm6();
Init_EPwm7();
Init_EPwm8();

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
EDIS;

//
// Step 5. User specific code, enable interrupts:
// Initialize counters:
//
EPwm1TimerIntCount = 0;
EPwm2TimerIntCount = 0;
EPwm3TimerIntCount = 0;
EPwm4TimerIntCount = 0;
EPwm5TimerIntCount = 0;
EPwm6TimerIntCount = 0;
EPwm7TimerIntCount = 0;
EPwm8TimerIntCount = 0;

//
// Enable CPU INT3 which is connected to EPWM1-3 INT:
//
IER |= M_INT3;

//
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
//
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
PieCtrlRegs.PIEIER4.bit.INTx4 = 1;
PieCtrlRegs.PIEIER5.bit.INTx4 = 1;
PieCtrlRegs.PIEIER6.bit.INTx4 = 1;
PieCtrlRegs.PIEIER7.bit.INTx4 = 1;
PieCtrlRegs.PIEIER8.bit.INTx4 = 1;

//
// Enable global Interrupts and higher priority real-time debug events:
//
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM


}




//
// End of file
//

Hi Dave,

Here's what is happening when you use a PHN value >= 3334. According to your code, the actual phase value programmed in the PWM4 phase register (TBPHS) is

PHN * 3 = 3334*3 = 10002. This is obviously greater than your programmed period (TBPRD) value of 10000. As a result on the next sync the PWM4 counter (TBCTR4) jumps to 10002 and counts up. TBCTR4 keeps counting up until the next sync event comes in 10000 cycles later i.e. when TBCTR4 = 20002. At this point TBCTR4 again jumps to 10002 and is stuck between these two values (10002 and 20002). As a result you do not see any output on PWM4.

For a 4-phase system a 90 deg phase shift among phases is commonly used. This would mean that your PHN value should be clamped to 10000/4 = 2500. If, however, you want the phase shift to go beyond 90 deg phase shift among phases, you will have to modify your TBPHS calculations. In this case, you can workaround this problem by wrapping around the PHN*3 number once it starts going above 10000.

I hope this helps.

Hrishi

Thanks, that is of great help.

I appreciate your help.

My next challenge is find a way to get the chopping frequency in the 5Khz area. The chopper is putting out a frequency near 1Mhz. I do not see a way of reducing it to my needs with the various clock options.

If I cannot use the chopper as is is there a way to gate the outputs A & B with s signal from another PWM channel so I can have better control of duty cycle and frequency? I don't want to have to use external logic to perform this function.

If this need to be in a new thread let me know.

Thanks for your help.