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TMS320F28034: Wake up device from halt mode failed

Part Number: TMS320F28034
Other Parts Discussed in Thread: CONTROLSUITE

Dear C2000 expert,

Currently I'm trying to wake up F28034 from halt mode via pulling low the GPIO25, but sometimes it's failed, and somtimes it's OK. 

My code is referenced with demo code in controlsuite: (C:\ti\controlSUITE\device_support\f2803x\v130\DSP2803x_examples_ccsv5\lpm_haltwake), please see attached for more details.

/*
 * f2803x_lpm.c
 *
 *  Created on: 2018-4-16
 *      Author: Administrator
 */

#include "global.h"
#include "Driver.h"
#include "General.h"
#include "f2803x_lpm.h"

__interrupt void f2803x_lpm_wake_isr(void);

void init_f2803x_lpm(void)
{
	EALLOW;
	//GpioCtrlRegs.GPAPUD.bit.GPIO25 = 1;
	//GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 0;    //GPIO
	GpioCtrlRegs.GPADIR.bit.GPIO25 = 0;     // 0 - input mode; 1 - output mode
	GpioIntRegs.GPIOLPMSEL.bit.GPIO25 = 1;  // Choose GPIO8 pin for wakeup
	EDIS;

	// Interrupts that are used in this example are re-mapped to
	// ISR functions found within this file.
	EALLOW;  // This is needed to write to EALLOW protected registers
	PieVectTable.WAKEINT = &f2803x_lpm_wake_isr;
	EDIS;

}

void f2803x_lpm_handler(void)
{
	static TIMER_T tTime;      //3Sʱ���ʱ
	App_TimeBase(MS_BASE, &tTime);

	if(GpioDataRegs.GPADAT.bit.GPIO25 == 1)
	{
		if(tTime.DelayTime >= 1000)
		{
			// Enable CPU INT1 which is connected to WakeInt:
			IER |= M_INT1;

			// Enable WAKEINT in the PIE: Group 1 interrupt 8
			PieCtrlRegs.PIEIER1.bit.INTx8 = 1;
			PieCtrlRegs.PIEACK.bit.ACK1 = 1;
			// Enable global Interrupts:
			EINT;   // Enable Global interrupt INTM

			// Write the LPM code value
			EALLOW;
			if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 1) // Only enter low power mode when PLL is not in limp mode.
			{
				SysCtrlRegs.LPMCR0.bit.LPM = 0x0002;   // LPM mode = Halt
			}
			EDIS;

			// Force device into HALT
			__asm(" IDLE");                         // Device waits in IDLE until falling edge on GPIO0/XNMI pin
		}
	}
	else
	{
		tTime.DelayTime = 0;
	}
}

__interrupt void f2803x_lpm_wake_isr(void)
{
	//GpioDataRegs.GPATOGGLE.bit.GPIO1 = 1;	// Toggle GPIO1 in the ISR - monitored with oscilloscope
	PieCtrlRegs.PIEIER1.bit.INTx8 = 1;
	PieCtrlRegs.PIEACK.bit.ACK1 = 1;
}
f2803x_lpm.h

-          init_f2803x_lpm is initialization function

-          f2803x_lpm_handler is executed in background loop

-          f2803x_lpm_wake_isr is interrupt service routine

In my solution, when does GPIO25 goes to high level, then device enter into halt mode(I see the current decreased), but when the GPIO25 goes to low level state, sometimes device won't wake up.

Can you please help on this?

  • Jack,

    Can you provide a few screen captures of your wake signal as well as the GPIO25 during entry and exit?
    How long is your wake pulse? Does it satisfy the minimum wake-pulse as identified in the HALT Mode Timing Requirements Table in the Datasheet SPRS584?

    Thanks,
    Mark
  • Hey Mark,

    I didn't use wake pulse to wake up device, I'm trying to wake up device by connecting the GPIO25 to GND, there is no pulse generated. Is it possible?
  • Hey Mark,

    The device could be wake up by using low level pulse. I see the time requirement, the typical value of toscst is 10ms, but I can't find what the value of tc(OSCCLK) is in datasheet? Can you please provide it?

  • Jack,

    Halt mode requires a low going pulse in order to wake. The Falling edge asynchronously restarts the clocking systems, after allowing the clocks to start up again, the rising edge will release the device from halt mode and the device will execute it's wakeup procedure. No rising edge means no wake up.

    tc(OSCCLK) is the cycle time of OSCCLK - which is the input clock source as selected by CLKCTL.OSCCLKSRCSEL. If this input clock source is INSTOSC1, this is the cycle time of INTOSC1, if you are using XCLKIN, or the on chip XTAL (using X1/X2), it will be the cycle time of that clock source. I see that this is not defined at all in the document and I will file a ticket to ensure that it is. Check out Figure 6-7 Clock Tree (www.ti.com/.../detailed-description )in the Datasheet to see the sources of OSCCLK

    t(OSCST) is the oscillator startup time, which is defined in Table 5-4 Reset (XRSn) Switching Characteristics. ( www.ti.com/.../specifications )

    Thanks,
    Mark
  • Mark,

    Thanks for the clear explanation.