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TMS320F28035: PWM tolerance

Wayne Huang
Genius 16795 points

Part Number: TMS320F28035

Champs,

Our customer requests us to calculate the tolerance of PWM duty.

I following this criteria to determine the tolerance, please help to check it.

http://processors.wiki.ti.com/index.php/PLL_Jitter_on_C28x_Devices

 

Using formula 1

  • Input clock frequency = 20 MHz +/- 30ppm.
  • PLL Output clock Frequency = 120 MHz
  • SYSCLKOUT = (PLL Output/2) = 60MHz

This means:

1.    Input clock jitter => 20 MHz, 30ppm => 1.5 ps

2.    [pll_output_clock_period * 0.05 * sqrt(2)] = (1/120 MHz) * .05 * sqrt(2) = 589.25 ps

3.    PLL Jitter = MAX (1.5 ps, 589.25 ps) = 589.25 ps

PWM resolution: 16.67ns, PWM worst tolerance: 589.25ps / 16.67ns * 100 = 3.53%

 

 

Is our estimation correct?

Wayne

  • 0
    TI__Mastermind 42195 points

    Wayne,

    in your first calculation I think you should use a total of 60PPM because it is a +/- number(resulting in: 3.0 pS), but it is significantly less than PLL's jitter, so it shouldn't be an issue.

    Worst case, if your PWM pulse that was 1 system clock wide... Then yes, it could be off by upto 3.53%.

    But practically the PWM pulse will be 100, 1000 or even 10000 clock cycles wide and the jitter will roughly cancel out.

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    TI__Genius 16795 points
    Cody,

    I don't quite understand what you mean by "cancel out" here.
    Does it mean that if the PWM period is 100 clock cycles wide, then the tolerance should be viewed as 3.53%/100 = 0.0353%?
    Is this what you meant?

    Wayne
  • 0 in reply to Wayne Huang
    TI__Mastermind 42195 points

    Wayne, 

    It is my understanding that clock jitter is random and has roughly a Gaussian distribution. Simplifying that a bit, roughly half of your clock pulses will be longer than expected and the other half of your clock cycles will be shorter than expected. It is then safe to assume that over a period of time most of the jitter will cancel out. 

    I can't say for certain that the jitter will cancel out after x number of clock cycles, because that depends on the system. In my experience with the PWM, customers do not often complain about clock or PLL induced jitter on the PWM. 

    If your customer would like to see the effects of clock jitter, they should be able to use a function generator to provide a clock to the device and intentionally add jitter. Note: you will need a pretty good function generator or its signal may jitter too much for the measurement.

    Now to answer your question: The 3.53%/100 is the best case jitter, this assumes that all of the previous cycles cancel out and you only have uncertainty from the last clock cycle. I doubt you'll ever see a number that good, this is a system dependent factor and the customer will simply have to test to see the total jitter their PWM has. Again the distribution should be roughly Gaussian and most of the jitter should cancel out.

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    TI__Genius 16795 points
    Cody,

    Thank you.

    Wayne