TMS320F28377S: EPWM SYNC chain destroys ADCSOC event generation

fmdhr

Part Number: TMS320F28377S

Hi,

I observe the following interesting behaviour:

First, I have a PWM control task that is splitted in two parts, and so I use two ADC conversions: One at the zero event (TBCTR = 0) and another at the period event, while PWM counter mode of the two modules used is UP-DOWN. Works fine, I get 2 ADC interrupts per period (ratio 1:1).

Second, I have to synchronize my PWM to an external signal. I use a third EPWM module as source for an internal sync signal that is compared to the external signal using ECAPs. This third EPWM (EPwm1) generates the SYNCI signals for the other two EPWMs (7 and 8). Synchronisation is done by an adjustment of the period of Epwm1, and the sync chain (see Figure 13-7. Time-Base Counter Synchronization Scheme in the TRM SPRUHX5E.pdf) forwards the synchronisation to the other two modules. Also works fine.

However, as soon as the synchronisation runs (external signal on), I get much less ADC conversions/interrupts on zero than on period, the ratio is now about 1/sqrt(2) : 1. Since I use TBPHS = 0, I expect that the ZERO event (generation) takes place in every cycle (TBCTR = TBPHS = 0!), but obviously it does not.

As a workaround, I used Epwm1 for the ADCSOC generation, and all is fine again.

I did not find any hint for this behaviour in the TRM.

Frank

Here some code snippets for explanation:

    /* Time Base Control Register (TBCTL) - set counter mode, divider */
    epwm_regs->TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; /* count up / down */
    epwm_regs->TBCTL.bit.PHSEN = TB_ENABLE;         /* enable phase loading */
    epwm_regs->TBCTL.bit.PRDLD = 0;                 /* on CTR = 0 and SYNC */
    epwm_regs->TBCTL.bit.SYNCOSEL = 0;              /* SYNCO = SYNCI */
    epwm_regs->TBCTL.bit.HSPCLKDIV = TB_DIV1;       /* clock divs = 1 */
    epwm_regs->TBCTL.bit.CLKDIV = TB_DIV1;
    epwm_regs->TBCTL.bit.FREE_SOFT = 0x02;          /* 0x02 = free run */
    /* Time Base Control Register 2 (TBCTL2) */
    epwm_regs->TBCTL2.all = 0x0000;     /* default = 0 */
    /* Time Base Counter Register (TBCTR) - clear counter */
    epwm_regs->TBCTR = 0x0000;
    /* Time Base Status Register (TBSTS) - clear events */
    epwm_regs->TBSTS.bit.CTRMAX = 1;
    epwm_regs->TBSTS.bit.SYNCI = 1;
    /* Time Base Phase High (TBPHS) */
    epwm_regs->TBPHS.all = 0x00000000;

This does not work for a synchronised EPWM module:

    /* generate SOC A event on zero */
    epwm_regs->ETSEL.bit.SOCAEN = 1;           /* enable SOC on A group */
    epwm_regs->ETSEL.bit.SOCASEL = 1;           /* 1 = SOC on CTR = ZRO */

over 7 years ago

0 Hrishi Nene over 7 years ago

TI__Genius 10820 points

Hi,

I think I will need some more details. How are you figuring out that the ADC conversions on 0 are the ones that are being missed when external sync is ON? Also, is the external sync periodic? Is it possible for this ext sync to come in at a rate higher than the programmed PWM period?

Would it be possible for you to draw up the PWM waveforms along with the time base counter waveforms for the desired and observed results?

Thanks.

Hrishi

0 fmdhr over 7 years ago in reply to Hrishi Nene

Expert 1530 points

Hrishni,

to your questions:

Hrishi Nene said:
How are you figuring out that the ADC conversions on 0 are the ones that are being missed when external sync is ON?

I just count the interrupts in both control tasks T1 (SOCA on zero) and T2 (SOCB on period)

Hrishi Nene said:
Also, is the external sync periodic? Is it possible for this ext sync to come in at a rate higher than the programmed PWM period?

Yes and yes. Both signals have nearly the same period, and they differ only slightly due to the different quartz clock generators.

I have the following explanation: Due to the synchronisation by the sync chain the TBCTR 7 cannot count down to zero, because it is reloaded with TBPHS = 0. This happens if TBPRD1 - 1 < 2 * TBPRD7 due to the period adjustment of PWM1. I guess that (by the hardware) the SOC event is generated if CTR=0 is reached by counting, but not if CTR is set to 0 by synchronisation. IMHO there's no fix without changing the hardware, but the behaviour should be mentioned in the TRM.

Hrishi Nene said:
Would it be possible for you to draw up the PWM waveforms along with the time base counter waveforms for the desired and observed results?

You can find a sketch in the file attached, I hope it is readable.pwm_timing_201805030907.pdf

Regards,

Frank

0 Hrishi Nene over 7 years ago in reply to fmdhr

TI__Genius 10820 points

Hi Frank,

Thank you for the explanation and the sketch. I believe if you use the same external sync signal to sync PWM7 and PWM8 time-bases, the number of SOCs should match. However, I understand that this may not be what you desire because you want to capture the period of the external signal and use it for the PWMs. The other option is to use a value of '1' in the TBPHS registers for PWM7 and PWM8. Also, select the counters for PWM7 and PWM8 to count down after a sync event (TBCTL[PHSDIR]).

Let me know how this goes.

Hrishi

0 fmdhr over 7 years ago in reply to Hrishi Nene

Expert 1530 points

Hi Hrisni,

sorry for my delayed response.

EPWM8 is not involved in the event generation, it is just needed for the second half bridge (of course, it must be synchronized too).

I did as you recommended and tried

epwm_regs->TBCTL.bit.PHSDIR = 0;

epwm_regs->TBPHS.all = 0x00010000;

for EPWM7 and EPWM8, and I get the same number of ADC SOCs (and interrupts) - just as my old solution with EPWM1 as SOC source and TBPHS = 0 did (see above).

I did not investigate in detail, how the different phase loadings influence the quality of the synchronisation algorithm, but generally, both approaches work well.

Thanks & regards,

Frank

0 Hrishi Nene over 7 years ago in reply to fmdhr

TI__Genius 10820 points

Hi Frank,

Could you please clarify one thing. Are you saying that using a TBPHS value of 1 and configuring the slave time-base counter to count down after a sync event works just as the other solution of using PWM1 ADCSOC?

Also, should we consider that this issue has been resolved?

Thanks.
Hrishi

0 fmdhr over 7 years ago in reply to Hrishi Nene

Expert 1530 points

Hrishi,

Hrishi Nene said:

Could you please clarify one thing. Are you saying that using a TBPHS value of 1 and configuring the slave time-base counter to count down after a sync event works just as the other solution of using PWM1 ADCSOC?

Yes, ADCSOC events are generated in both cases, and using the synchronized EPWM itself for event generation may be the more general solution, rather than my extra EPWM1. The different timing has to be taken into account, e.g. by subtraction of the additional cycle from the period.

Hrishi Nene said:

Also, should we consider that this issue has been resolved?

From my point of view, yes. May be you want to place a notice in the TRM, that event generation for CTR=ZRO may fail for synchronisation with TBPHS = 0 for both TBCTL.bit.PHSDIR 0 and 1. And may be your hardware designers want to make a fix in one of the next releases of the EPWM peripheral.

Thanks & regards, and sorry for the misspelling of your name in my last mail,

Frank

0 Hrishi Nene over 7 years ago in reply to fmdhr

TI__Genius 10820 points

Frank,

Thank you for the update and the feedback.

Hrishi

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TMS320F28377S: EPWM SYNC chain destroys ADCSOC event generation