CCS/LAUNCHXL-F28069M: Generate PWM INT each 5th event trigger

Hi Ahmed,

I see a similar thread posted by you. Did the original post not resolve your query?
e2e.ti.com/.../680583

Thanks
Vasudha

Hi Vasudha,
My first idea was to generate another PWM2 and synchronize it with the first one PWM1 each 2nd event, then make PWM2 generate interrupt each 3rd event. this way the interrupt generated each 6th event. Unfortunately, I couldn't do that as i didn't know how to synchronize PWM2 with PWM1 each 2nd event (to have half the frequency). I went back to TRM as you suggested but i couldn't find any guide on how to do that.

Thank you
Ahmed

Great point Cody !
actually what I'm doing now is to generate a software interrupt each nth event by adding a counter in PWM ISR. BUT the problem is this approach consumes extra processing cycles that is critical for my application (Clear interrupt flag, Acknowledge, then count and check if the 6th event happened) and even there is latency between raising the software interrupt flag and starting the software ISR and I don't know the reason for this latency. Here is part of my code:

interrupt void epwm1_isr(void) 
{ // Clear INT flag for this timer
EPwm1Regs.ETCLR.bit.INT = 1; 
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
//count cycles to update control
cycle_counter++;
if (cycle_counter == max_cycle+1)
{
// Set Software INT flag INT4.4
PieCtrlRegs.PIEIFR4.bit.INTx4 = 1;
cycle_counter = 1;
}

}

interrupt void Software_ISR(void) // main interrupt function, the outer loop is global state machine
{

IER |= M_INT3; 
PieCtrlRegs.PIEIER3.bit.INTx1 = 1; // Set group priority by adjusting PIEIER2 to allow INT3.1 to interrupt current ISR
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
asm(" NOP"); // Wait one cycle
EINT;

**software ISR code

DINT

}

So I prefer if there is a hardware solution that could save me some processing time.
As per your suggestion of generating another PWM with lower frequency. well, for my application the PWM period changes frequently and abruptly, so I cannot rely just on aligning the two PWM by setting the period. I was thinking of somehow synchronizing them together so, for instance, the zero of the second PWM is synchronized with the second zero of the first PWM, so no matter what the period changes for the first PWM, I can guarantee INT each 6th zero

Do you have ideas on how to do that?

Thank you
Ahmed

Edited 5/4/18 10:25 CST

I replied too quickly, to shortly answer your first response to Vasudha: The sync pulse will come every cycle if it is enabled... There have been people who work around this by using SWSYNC, but my understanding is that it wasn't as trivial as it sounds.

_________________________________

Ahmed,

the synchronization scheme is discussed in the ePWM chapter, it is included as part of the Time-Base submodule's subsection(3.2.2).

You will need to configure the SYNCO pulse of your one PWM and select that same signal on the SYNCI signal of the next PWM. You will also need to enable phase loading using TBCTL.PHSEN or the pulse will be ignored. TBPHS can be used to apply a phase shift if desired.

When testing your system I recommend that you intentionally add a phase offset then correct it to ensure your sync chain is setup correctly.

The full details of all of these features and more can be found inside the TRM that was linked to previously.

Regards,
Cody 

Cody,
for the first suggestion:
Actually my code takes approximately the whole cycles to complete and that's why i need to delay the interrupt to the 6th event (basically my PWM frequency is 0.8MHz to 1.5MHz and the SYSCLK is 90MHz and i have limited time to process) so I think if I just nested the code in if statement within PWM ISR, I'll definitely miss one interrupt of the PWM if I'm working with 1.5MHz PWM. So that's why i took my main code outside the PWM ISR. this way if PWM interrupt happens, the program jumps to the PWM ISR and increase the counter then go back again to the Software interrupt.

I don't fully understand you second suggestion. I actually update the PRD on the 6th cycle but sometimes in my code I need to update the PRD in both 5th cycle then again in 6th cycle and if so the alignment with the low frequency PWM is not guaranteed i guess? . Anyway, i will try this suggestion see if it still gives good performance.

Thanks cody
Ahmed

Ahmed,

yeah, with ISR frequencies that high, the first method would likely be too burdensome. 

The second method will probably degrade system performance in some way, but often times customers over constrain their design. I won't know enough about your system to tell you if it can tolerate a lower refresh rate on your PWM's period, but you should be able to measure its effect.

Regards,
Cody