Part Number: TMS320F28375S
Hi,
planning to use 8MHz oscillator (OSCCLK) with the following PLL settings to produce 200MHz (PLLSYSCLK)
SYSPLLMULT.IMULT = 25 (0x19)
SYSPLLMULT.FMULT = 0 (0x0)
SYSCLKDIVSEL.PLLSYSCLKDIV = 0 (0x0) for /1
PLLRAWCLK is also within the limits (120 to 400MHz)
My question: Is it ok to use a lower OSCCLK to produce a max PLLSYSCLK. would there be any implications (ex: increase in PLL setting time, jitter etc.) against using a higher OSCCLK say 25MHz.
Thanks in advance!
Regards,
Muthu A
