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CCS/TMS320F28379D: Comparator to produce trip connect with Digital compare to EPWM

Min Zhang
Intellectual 450 points
Part Number: TMS320F28379D
Other Parts Discussed in Thread: DESIGNDRIVE

Tool/software: Code Composer Studio

Hi

I am try to use a comparator to produce two trip signals: one from the comparator high and one from comparator low. I use these two signals to connect to Digital compare modules to produce DCAEVT2 and DCBEVT2 digital compare signals. After that, I connect TZ1 and TZ2 to these digital compare signals. TZ1 and TZ2 are set by using EPWM action qualifier. However, i couldn't see the right PWM output. 

I will upload the code fragment in here. 

digital compare code fragment

//
// configure TRIP4 to high trips from comparator 1
// configure TRIP5 to low trips from comparator 1
//
// Clear everything first
//

EPwmXbarRegs.TRIP4MUX0TO15CFG.all = 0x0000;
EPwmXbarRegs.TRIP4MUX16TO31CFG.all = 0x0000;
EPwmXbarRegs.TRIP5MUX0TO15CFG.all = 0x0000;
EPwmXbarRegs.TRIP5MUX16TO31CFG.all = 0x0000;

//
// Enable Mux for input of CMPSS1H and 1L
//
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 0; //cmpss1 CTRIPH
EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX1 = 0; //cmpss1 CTRIPL

// Disable all the muxes first
EPwmXbarRegs.TRIP4MUXENABLE.all = 0x0000;
EPwmXbarRegs.TRIP5MUXENABLE.all = 0x0000;
// Enable Mux4 to TRIP4
// Enable Mux0 to TRIP5

EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1;
EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX1 = 1;

// EPwm2 trip 4 DC A low ---> DCAEVT2
EPwm2Regs.DCTRIPSEL.bit.DCALCOMPSEL = 3; // Trip 4 DC A low
EPwm2Regs.TZDCSEL.bit.DCAEVT2 = 4; // DCAL high DCAH don't care
EPwm2Regs.DCACTL.bit.EVT2SRCSEL = 0; // No filter
EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = 1; // Asynchronously

// EPwm2 trip 5 DC B low ---> DCBEVT2
EPwm2Regs.DCTRIPSEL.bit.DCBLCOMPSEL = 4; // Trip 5 DC B low
EPwm2Regs.TZDCSEL.bit.DCBEVT2 = 4; // DCBL high DCBH don't care
EPwm2Regs.DCBCTL.bit.EVT2SRCSEL = 0; // No filter
EPwm2Regs.DCBCTL.bit.EVT2FRCSYNCSEL = 1; // Asynchronously

// EPwm3 trip 4 DC A low ---> DCAEVT2
EPwm3Regs.DCTRIPSEL.bit.DCALCOMPSEL = 3; // Trip 4 DC A low
EPwm3Regs.TZDCSEL.bit.DCAEVT2 = 4; // DCAL high DCAH don't care
EPwm3Regs.DCACTL.bit.EVT2SRCSEL = 0; // No filter
EPwm3Regs.DCACTL.bit.EVT2FRCSYNCSEL = 1; // Asynchronously

// EPwm3 trip 5 DC B low ---> DCBEVT2
EPwm3Regs.DCTRIPSEL.bit.DCBLCOMPSEL = 4; // Trip 5 DC B low
EPwm3Regs.TZDCSEL.bit.DCBEVT2 = 4; // DCBL high DCBH don't care
EPwm3Regs.DCBCTL.bit.EVT2SRCSEL = 0; // No filter
EPwm3Regs.DCBCTL.bit.EVT2FRCSYNCSEL = 1; // Asynchronously

// Connect the digital compare to PWM actions
EPwm2Regs.AQTSRCSEL.bit.T1SEL=1; // DCAEVT2 connect to T1
EPwm2Regs.AQTSRCSEL.bit.T2SEL=3; // DCBEVT2 connect to T2
EPwm3Regs.AQTSRCSEL.bit.T1SEL=1; // DCAEVT2 connect to T1
EPwm3Regs.AQTSRCSEL.bit.T2SEL=3; // DCBEVT2 connect to T2

// Clear any spurious OV trip
EPwm2Regs.TZCLR.bit.DCAEVT2 = 1;
EPwm2Regs.TZCLR.bit.DCBEVT2 = 1;
EPwm3Regs.TZCLR.bit.DCAEVT2 = 1;
EPwm3Regs.TZCLR.bit.DCBEVT2 = 1;

EDIS;

//
// EPWM2 for the phase v
//
//
// Setup TBCLK
//
EPwm2Regs.TBCTL.bit.HSPCLKDIV=1; // divide by 2
EPwm2Regs.TBCTL.bit.CLKDIV=2; // divide by 4 12.5MHz EPWMCLOCK
EPwm2Regs.TBCTL.bit.CTRMODE=0; // up mode
EPwm2Regs.TBCTL.bit.PHSEN=0; // disable phase loading

//
// Enable PWM
//
EPwm2Regs.TBPRD = 62499; // 200Hz PWM
EPwm2Regs.TBPHS.bit.TBPHS= 0; // phase is zero
EPwm2Regs.TBCTR= 0; // clear counter

// EPWM2 dead band
//
EPwm2Regs.DBCTL.bit.OUT_MODE=3; // DBM is fully enabled
EPwm2Regs.DBCTL.bit.POLSEL=2; // Active high complementary
EPwm2Regs.DBCTL.bit.IN_MODE=0; // EPWMA is the source for both falling edge and rising edge delay
EPwm2Regs.DBRED.bit.DBRED=25; // deadtime 2us
EPwm2Regs.DBFED.bit.DBFED=25; // deadtime 2us

//
// EPWM3 for the phase w
//

//
// Setup TBCLK
//
EPwm3Regs.TBCTL.bit.HSPCLKDIV=1; // divide by 2
EPwm3Regs.TBCTL.bit.CLKDIV=2; // divide by 4 100MHz
EPwm3Regs.TBCTL.bit.CTRMODE=0; // up mode
EPwm3Regs.TBCTL.bit.PHSEN=0; // diable phase loading

//
// Enable PWM
//
EPwm3Regs.TBPRD = 62499; // 200Hz
EPwm3Regs.TBPHS.bit.TBPHS= 0; // phase is zero
EPwm3Regs.TBCTR= 0; // clear counter

//
// EPWM3 dead band
//
EPwm3Regs.DBCTL.bit.OUT_MODE=3; // DBM is fully enabled
EPwm3Regs.DBCTL.bit.POLSEL=2; // Active high complementary
EPwm3Regs.DBCTL.bit.IN_MODE=0; // EPWMA is the source for both falling edge and rising edge delay
EPwm3Regs.DBRED.bit.DBRED=25; // deadtime 2us
EPwm3Regs.DBFED.bit.DBFED=25; // deadtime 2us

// PWM action qualifier
EPwm2Regs.AQCTLA2.bit.T1U = 2; // 2A high
EPwm2Regs.AQCTLB2.bit.T1U = 1; // 2B low
EPwm3Regs.AQCTLA2.bit.T1U = 1; // 3A low
EPwm3Regs.AQCTLB2.bit.T1U = 2; // 3B high

EPwm2Regs.AQCTLA2.bit.T2U = 1; // 2A low
EPwm2Regs.AQCTLB2.bit.T2U = 2; // 2B high
EPwm3Regs.AQCTLA2.bit.T2U = 2; // 3A high
EPwm3Regs.AQCTLB2.bit.T2U = 1; // 3B low

  • 0
    TI__Mastermind 28275 points

    Hi Ming,

    I haven't looked through your code but can you provide a little more detail? What output do you expect and what output are you seeing?

  • 0 in reply to Frank Ankapong
    Intellectual 450 points
    I do it simply, i have the LEM output default connect to ADCPIN A2 which is comparator 1 high positive. The zero state of the ADC result is 2048. I wrote 2000 here to have a output on PWM. It should be PWM2A on PWM 2B off PWM 3A off PWM 3B on . However, i see a weriod result with PWM 2A 2B 3A both 3V with PWM 3B 6V. Which is rediculous.
  • 0 in reply to Frank Ankapong
    Intellectual 450 points
    It just the code fragement for the PWM and digital compare , the comparator and other code i didnt put it on.
  • 0 in reply to Min Zhang
    TI__Mastermind 28275 points
    Min,

    I'm not following your explanation. Not sure what the ADC has to do with this. Is it measuring the voltage on the comparator positive input? How are you driving the negative input of the comparator?
  • 0 in reply to Frank Ankapong
    Intellectual 450 points
    I am using the DesignDRIVE board with 28379D core. There is a LEM current sensor on the board, it connect to the ADCINA2 pin default. That pin is connect to the comparator 1P default as well. Therefore, i use DAC in the comparator high inverting and low inverting part to produce two trip signals. These trip signal is transfer to the muxbar and connect to digital compare . The digital compare is connect to PWm action qualifier by using TZ1 and TZ2 . And the actions is setted by using the action qualifier. In my example, i got zero current result on ADC which is default to be 2048 (output with 1.65V shift set by LEM sensor). I set the comparator high side DAC equal to 2000. Therefore, a trip signal is provided and transfer to the digital compare. The PWm configurations should be PWM2A on PWM 2B off, PWM 3A off PWM 3B on. However, i see the wrong result in the PWM output.
  • 0 in reply to Min Zhang
    TI__Mastermind 28275 points
    Ok Min, i think I'm getting the picture now. Looks like you are sending the signal through multiple PWM modules. Without seeing any waveforms, it will be hard to just look at the configuration code and tell you what is wrong. Your problem is most likely coming from a misconfigured PWM submodule. However, you can at least narrow it down: The CMPSS can drive the GPIO directly without going through the PWM. The DC submodule can drive the PWM output directly without involving the AQ submodule. Can you look at the CMPSS and DC submodule outputs separately to see if it's what you expect?