Dear all,
By viewing the F28335.cmd and DSP2833x_Headers_nonBIOS.cmd file, I have some questions about CSM_PWL:
CSM_PWL : origin = 0x33FFF8, length = 0x000008
Both page1 and page0 are allocated space, the address is the same, and the compiler will not complain. Which area will be allocated to it after compilation? Will this cause the chip to be locked?
thank you.