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CCS/TIDM-1000: Testing issue

Part Number: TIDM-1000

Tool/software: Code Composer Studio

Hi Sir

We followed the Reference Design of TIDM-1000 to estimate Vienna PFC performance.There are questions below:

1. When build level set to 1~3,Could the EVM  run in 208VL-L 1.2KW and 400VL-L 2.4KW?

2. Whatever build level is in 1~4,the EVM must run in CCS debug mode.

    Could the EVM run automatically after code is programed? If yes,How to do?

Best regards,

Harry

  • Harry as this is demonstration EVM, we typically do not enable auto starting, so the user can first make sure everything is good with debug scenario.

    Then when they do need to run the code independently, the only action they need to do is put "clearTrip" to 1 , the user can add a code to start PFC action and set Vbus accordingly. 

    pseudo code

    if(Vrms is in range)

    clearTrip=1; 

    set VbusRef accordingly

    else

    trip the converter and wait for Vrms to be in range.

    The code is already running in Flash , so there are no other changes required. 

  • 1. When build level set to 1~3,Could the EVM run in 208VL-L 1.2KW and 400VL-L 2.4KW?
    Please refer to the UG, it does specify the range on the very first page and is marker out clearly

    Three-Phase Input 208 VL-L 60 Hz, Output 600-V
    DC Nominal, 1.2 KW
    Three-Phase Input 400 VL-L 50 Hz, Output 700-V
    DC Nominal, 2.4 KW
  • Hi Manish

    We have seen the first page of UG and known the EVM capability.
    According to figure 16 of UG,the connecting load is seems fixed 500 Ohms.
    When we set build level set to 3, the Vbus could been adjusted to 600V and load was about 720W not 1.2KW.
    We thought the build level 1~3 not a completed control loop and not sure the load could been added to 1.2KW or not.
    we need to confirm the point and don't want to damage the EVM.
  • Hi Manish

    Thanks for your solution.Is it still run in CCS Debug mode?
    We don't want to start code executing via CCS Debug mode.
    Furthermore,when we set or monitored some variables via CCS Debug mode.
    We found communication was often break between control board and PC.
    Do you have any idea about it?
  • 1. Harry, yes the load can be changed. We provide one load value in the documentation so that at least the basic check is very repeatable. 

    2. Refer to section 3.1.1.3 in the following user guide

    make sure you have JTAG wire wound on a ferrite core, also removing the cap as mentioned in the doc helps with the connection issues. 

    For the best performance of this reference design, remove the capacitor connected between the isolated grounds on the control card, C26:A.

  • Also i appreciate your diligence in checking with us first :)